CY7C037V-25AC Cypress Semiconductor Corp, CY7C037V-25AC Datasheet - Page 11

• Manufacturer Part Number: CY7C037V-25AC
• Description: SRAM Chip Async Dual 3.3V 576K-Bit 32K x 18 25ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C037V-25AC

• Package: 100TQFP
• Timing Type: Asynchronous
• Density: 576 Kb
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 15 Bit
• Number Of I/o Lines: 18 Bit
• Number Of Ports: 2
• Number Of Words: 32K

Document #: 38-06078 Rev. *A
Switching Waveforms
Timing Diagram of Semaphore Contention
Semaphore Read After Write Timing, Either Side
Notes:
34. CE = HIGH for the duration of the above timing (both write and read cycle).
35. I/O
36. Semaphores are reset (available to both ports) at cycle start.
37. If t
A
A
A
0R
0L
0
SPS
0R
SEM
SEM
SEM
–A
R/W
I/O
R/W
R/W
–A
–A
OE
= I/O
is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
2
2L
2R
0
R
L
L
R
0L
= LOW (request semaphore); CE
t
SA
(continued)
VALID ADRESS
t
AW
R
= CE
WRITE CYCLE
t
t
PWE
SCE
t
L
SD
DATA
t
= HIGH.
MATCH
SPS
MATCH
[35, 36, 37]
t
IN
HA
VALID
[34]
t
HD
t
SWRD
t
SOP
t
SOP
READ CYCLE
t
SAA
VALID ADRESS
t
DOE
t
ACE
DATA
CY7C027V/028V
CY7C037V/038V
OUT
VALID
t
OHA
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