CS4299-JQ Cirrus Logic Inc, CS4299-JQ Datasheet - Page 3
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CS4299-JQ
Manufacturer Part Number
CS4299-JQ
Description
Audio Codec 1ADC / 1DAC 18-Bit/20-Bit 48-Pin LQFP
Manufacturer
Cirrus Logic Inc
Type
PCMr
Datasheet
1.CS4299-JQ.pdf
(52 pages)
Specifications of CS4299-JQ
Package
48LQFP
Adc/dac Resolution
18/20 Bit
Number Of Channels
1ADC /1 DAC
Sampling Rate
48 KSPS
Number Of Adc Inputs
8
Number Of Dac Outputs
3
Number Of Dacs
1
Operating Supply Voltage
3.3|5 V
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DS319PP6
LIST OF FIGURES
5. POWER MANAGEMENT ................................................................................................. 32
Figure 1. Power Up Timing ....................................................................................................... 8
Figure 2. Codec Ready from Startup or Fault Condition ........................................................... 8
Figure 3. Clocks ........................................................................................................................ 8
Figure 4. Data Setup and Hold.................................................................................................. 9
Figure 5. PR4 Powerdown and Warm Reset ............................................................................ 9
Figure 6. Test Mode .................................................................................................................. 9
Figure 7. AC-link Connections ................................................................................................ 10
Figure 8. Mixer Diagram.......................................................................................................... 12
Figure 9. AC-link Input and Output Framing ........................................................................... 13
Figure 10. Line Input (Replicate for Video and Aux) ...............................................................35
6. ANALOG HARDWARE DESCRIPTION ......................................................................... 35
7. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ............................................................39
8. GROUNDING AND LAYOUT ..........................................................................................39
9. PIN DESCRIPTIONS
10. PARAMETER AND TERM DEFINITIONS ....................................................................46
11. REFERENCE DESIGN .................................................................................................48
12. REFERENCES ..............................................................................................................49
13. PACKAGE DIMENSIONS .............................................................................................50
4.10 Stereo Analog Mixer Input Gain Registers (Index 10h - 18h) ................................. 24
4.11 Input Mux Select Register (Index 1Ah) ................................................................... 25
4.12 Record Gain Register (Index 1Ch) ......................................................................... 25
4.13 General Purpose Register (Index 20h) ................................................................... 26
4.14 3D Control Register (Index 22h) ............................................................................. 26
4.15 Powerdown Control/Status Register (Index 26h) ................................................... 27
4.16 Extended Audio ID Register (Index 28h) ................................................................ 28
4.17 PCM Front DAC Rate Register (Index 2Ch)
4.18 PCM L/R ADC Rate Register (Index 32h) .............................................................. 28
4.19 AC Mode Control Register (Index 5Eh) .................................................................. 29
4.20 Misc. Crystal Control Register (Index 60h) ............................................................. 29
4.21 S/PDIF Control Register (Index 68h) .....................................................................30
4.22 Vendor ID1 Register (Index 7Ch) ........................................................................... 31
4.23 Vendor ID2 Register (Index 7Eh) ........................................................................... 31
5.1 AC ’97 Reset Modes ................................................................................................ 32
5.2 Powerdown Controls ................................................................................................ 33
6.1 Analog Inputs ...........................................................................................................35
6.2 Analog Outputs ........................................................................................................37
6.3 Miscellaneous Analog Signals .................................................................................38
6.4 Power Supplies ........................................................................................................38
6.5 Reference Design ....................................................................................................38
5.1.1 Cold AC ‘97 Reset ....................................................................................... 32
5.1.2 Warm AC ’97 Reset ..................................................................................... 32
5.1.3 Register AC ’97 Reset ................................................................................. 32
6.1.4 Line-Level Inputs ........................................................................................35
6.1.5 CD Input .....................................................................................................35
6.1.6 Microphone Inputs ......................................................................................36
6.1.7 PC Beep Input ............................................................................................36
6.1.8 Phone Input ................................................................................................37
6.2.9 Stereo Outputs ...........................................................................................37
6.2.10 Mono Output .............................................................................................37
........................................................28
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