MACH210-15JC Lattice, MACH210-15JC Datasheet - Page 7

• Manufacturer Part Number: MACH210-15JC
• Description: CPLD MACH 2 Family 64 Macro Cells 66.6MHz EECMOS Technology 5V 44-Pin PLCC
• Manufacturer: Lattice

Specifications of MACH210-15JC

• Package: 44PLCC
• Family Name: MACH 2
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.6 MHz
• Number Of Product Terms Per Macro: 16
• Memory Type: EEPROM
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

FUNCTIONAL DESCRIPTION
The MACH210 consists of four PAL blocks connected
by a switch matrix. There are 32 I/O pins and 4
dedicated input pins feeding the switch matrix. These
signals are distributed to the four PAL blocks for efficient
design implementation. There are two clock pins that
can also be used as dedicated inputs.
The MACH210A inputs and I/O pins have built-in pull-up
resistors. While it is always a good design practice to tie
unused pins high, the 210A pull-up resistors provide
design security and stability in the event that unused
pins are left disconnected.
The PAL Blocks
Each PAL block in the MACH210 (Figure 1) contains a
64-product-term logic array, a logic allocator, 8 output
macrocells, 8 buried macrocells, and 8 I/O cells. The
switch matrix feeds each PAL block with 22 inputs. This
makes the PAL block look effectively like an independ-
ent “PAL22V16” with 8 buried macrocells.
In addition to the logic product terms, two output enable
product terms, an asynchronous reset product term,
and an asynchronous preset product term are provided.
One of the two output enable product terms can be
chosen within each I/O cell in the PAL block. All flip-flops
within the PAL block are initialized together.
The Switch Matrix
The MACH210 switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 8 I/O
feedback signals. The switch matrix distributes these
signals back to the PAL blocks in an efficient manner
that also provides for high performance. The design
software automatically configures the switch matrix
when fitting a design into the device.
The Product-term Array
The MACH210 product-term array consists of 64
product terms for logic use, and 4 special-purpose
product terms. Two of the special-purpose product
terms provide programmable output enable; one pro-
vides asynchronous reset, and one provides asynchro-
nous preset.
The Logic Allocator
The logic allocator in the MACH210 takes the 64 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to 16
product terms. The design software automatically
configures the logic allocator when fitting the design into
the device.
MACH210-7/10/12/15/20, Q-12/15/20
Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
The Macrocell
The MACH210 has two types of macrocell: output and
buried. The output macrocells can be configured as
either registered, latched, or combinatorial, with pro-
grammable polarity. The macrocell provides internal
feedback whether configured with or without the flip-
flop. The registers can be configured as D-type or
T-type, allowing for product-term optimization.
The flip-flops can individually select one of two clock/
gate pins, which are also available as data inputs. The
registers are clocked on the LOW-to-HIGH transition of
the clock signal. The latch holds its data when the gate
input is HIGH, and is transparent when the gate input is
LOW. The flip-flops can also be asynchronously initial-
ized with the common asynchronous reset and preset
product terms.
The buried macrocells are the same as the output
macrocells if they are used for generating logic. In that
case, the only thing that distinguishes them from the
output macrocells is the fact that there is no I/O cell
connection, and the signal is only used internally. The
buried macrocell can also be configured as an input
register or latch.
Output
M
M
M
M
M
M
M
M
10
12
14
0
2
4
6
8
Macrocell
Table 1. Logic Allocation
Buried
M
M
M
M
M
M
M
M
11
13
15
1
3
5
7
9
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
Available
Clusters
1
1
2
3
4
5
6
7
8
9
10
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
11
12
13
14
15
, C
, C
, C
, C
, C
2
2
3
4
5
6
7
8
9
10
, C
, C
, C
, C
, C
, C
, C
, C
11
, C
12
13
14
15
, C
, C
, C
, C
3
4
5
6
7
8
9
10
11
12
13
14
15
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