HD4074329S Renesas Electronics America, HD4074329S Datasheet - Page 56

• Manufacturer Part Number: HD4074329S
• Description: MCU 4-Bit HMCS400 CISC 20KB EPROM 3.3V/5V 64-Pin SDIP
• Manufacturer: Renesas Electronics America

Specifications of HD4074329S

• Package: 64SDIP
• Family Name: HMCS400
• Maximum Speed: 4.5 MHz
• Ram Size: 268 Byte
• Program Memory Size: 20 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 4 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 35
• On-chip Adc: 4-chx8-bit
• Operating Temperature: -20 to 75 °C
• Number Of Timers: 3

HD404328 Series
Write operations are valid from the second instruction execution cycle, so the STS instruction must be
executed after at least two cycles have been executed. The serial mode register is initialized to $0 by MCU
reset.
Serial Data Register (SRL: $006, SRU: $007): Eight-bit read/write register separated into upper and
lower digits located at sequential addresses. Data in this register is output from the SO pin, LSB first, in
synchronism with the falling edge of the transmit clock; and data is input, LSB first, through the SI pin at
the rising edge of the transmit clock. Input/output timing is shown in figure 31.
Data cannot be read or written during serial data transmission. If a read/write occurs during transmission,
the accuracy of the resultant data cannot be guaranteed.
52
Serial mode register (SMR): $005
Note: t
Bit 2
3
0
1
cyc
SMR
Bit 1 Bit 0
2
0
1
0
1
= 1.9074 s (with 4.1943-MHz crystal oscillator used at 1/8 division ratio)
0
1
0
1
0
1
0
1
1
Transmit clock selection
R1 /SCK pin mode selection
R1 /SCK Pin
SCK output
SCK output
SCK output
SCK output
SCK output
SCK output
SCK output
SCK input
0
0
0
Initial value: 0000,
R/W: W
Figure 30 Serial Mode Register
Clock Source
Prescaler
Prescaler
Prescaler
Prescaler
Prescaler
Prescaler
System clock
External clock
—
—
Prescaler Division
Ratio
2048
512
128
32
8
2
SMR
Bit 3
0
1
R1 port input or output pin
SCK input or output pin
0
R1 /SCK Pin
0
4096 t
1024 t
256 t
64 t
16 t
4 t
1 t
—
Transmit Clock
Period
cyc
cyc
cyc
cyc
cyc
cyc
cyc