A29010-70F AMIC, A29010-70F Datasheet - Page 9

• Manufacturer Part Number: A29010-70F
• Description: 58T1319
• Manufacturer: AMIC

Specifications of A29010-70F

• Memory Type: Flash - NOR
• Memory Size: 1Mbit
• Memory Configuration: 128K X 8
• Interface Type: Parallel
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 32
• Rohs Compliant: Yes

no longer latched. The system can determine the status of the
program operation by using I/O
Status" for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Programming is allowed in
any sequence and across sector boundaries. A bit cannot be
programmed from a "0" back to a "1 ". Attempting to do so
may halt the operation and set I/O
Polling algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is still "0".
Only erase operations can convert a "0" to a "1".
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which in
turn invokes the Embedded Erase algorithm. The device does
not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
(November, 2010, Version 1.4)
Note : See the appropriate Command Definitions table for
Increment Address
program command sequence.
algorithm in
Embedded
progress
Program
Figure 1. Program Operation
Last Address ?
Write Program
Programming
Verify Data ?
from System
7
Completed
Command
Sequence
Data Poll
or I/O
START
5
to "1", or cause the
Yes
Yes
6
. See "Write Operation
No
Data
8
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 2 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements for
the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
out of 50μs begins. During the time-out period, additional
sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50μs, otherwise the last address and command
might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase commands
can be assumed to be less than 50μs, the system need not
monitor I/O
Suspend during the time-out period resets the device to
reading array data. The system must rewrite the command
sequence
commands.
The system can monitor I/O
timer has timed out. (See the " I/O
section.) The time-out begins from the rising edge of the final
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O
Status" for information on these status bits.
Figure 2 illustrates the algorithm for the erase operation. Refer
to the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
WE
After the command sequence is written, a sector erase time-
pulse in the command sequence.
3
. Any command other than Sector Erase or Erase
and
any
7
, I/O
additional
6
AMIC Technology, Corp.
, or I/O
3
to determine if the sector erase
2
. Refer to "Write Operation
sector
3
A29010 Series
: Sector Erase Timer"
7
, I/O
addresses
6
, or I/O
2
. See
and