A29010-70F AMIC, A29010-70F Datasheet - Page 12

• Manufacturer Part Number: A29010-70F
• Description: 58T1319
• Manufacturer: AMIC

Specifications of A29010-70F

• Memory Type: Flash - NOR
• Memory Size: 1Mbit
• Memory Configuration: 128K X 8
• Interface Type: Parallel
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 32
• Rohs Compliant: Yes

Write Operation Status
Several bits, I/O
A29010 to determine the status of a write operation. Table 5
and the following subsections describe the functions of these
status bits. I/O
determining whether a program or erase operation is complete
or in progress. These three bits are discussed first.
I/O
The
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend.
valid after the rising edge of the final
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O
This I/O
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O
The system must provide the program address to read valid
status information on I/O
protected sector,
approximately 2μs, then the device returns to reading array
data.
During
produces a "0" on I/O
is complete, or if the device enters the Erase Suspend mode,
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in a
sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O
After an erase command sequence is written, if all sectors
selected for erasing are protected,
active for approximately 100μs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O
complement to true data, it can read valid data at I/O
the following read cycles. This is because I/O
asynchronously with I/O
asserted low. The
Algorithms) figure in the "AC Characteristics" section
illustrates this. Table 5 shows the outputs for
I/O
(November, 2010, Version 1.4)
Data
7
7
. Figure 3 shows the
: Data Polling
Data
Polling produces a "1" on I/O
7
7
the complement of the datum programmed to I/O
the
status also applies to programming during Erase
Polling bit, I/O
Embedded
2
7
, I/O
, I/O
Data
Data
3
7
, I/O
6
. When the Embedded Erase algorithm
7
0
and I/O
Data
7
.
. If a program address falls within a
- I/O
Polling Timings (During Embedded
5
, I/O
Erase
7
Polling on I/O
, indicates to the host system
6
Polling algorithm.
6
while Output Enable (
, and I/O
2
7
each offer a method for
algorithm,
7
has changed from the
.This is analogous to the
Data
7,
are provided in the
WE
Polling on I/O
7
Data
Data
is active for
7
Data
pulse in the
may change
Polling on
7
Polling is
- I/O
OE
Polling
0
7
) is
on
is
7
7
.
.
11
Note :
1. VA = Valid address for programming. During a sector
2. I/O
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
I/O
No
7
7
should be rechecked even if I/O
may change simultaneously with I/O
Figure 3. Data Polling Algorithm
Read I/O
Read I/O
Address = VA
Address = VA
I/O
I/O
I/O
START
7
7
FAIL
= Data ?
= Data ?
5
AMIC Technology, Corp.
= 1?
7
7
-I/O
- I/O
Yes
No
No
0
0
A29010 Series
5
= "1" because
Yes
Yes
5
.
PASS