SC28L194A1A NXP Semiconductors, SC28L194A1A Datasheet - Page 20

• Manufacturer Part Number: SC28L194A1A
• Description: UART Interface IC 3V-5V 4CH UART INTEL/MOT INTRF
• Manufacturer: NXP Semiconductors
• Type: Quad UART for 3.3 V and 5 V supply voltager

Specifications of SC28L194A1A

• Number Of Channels: 4
• Data Rate: 460.8 Kbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current: 30 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: PLCC-68
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / Rohs Status: Details
• Other names: SC28L194A1A,512

Philips Semiconductors
Table 6. RxCSR and TxCSR - Receiver and Transmitter Clock Select Registers
Both registers consist of single 5 bit field that selects the clock source for the receiver and transmitter, respectively. The unused bits in this
register read b’000. The baud rates shown in the table below are based on the x1 crystal frequency of 3.6864MHz. The baud rates shown below
will vary as the X1 crystal clock varies. For example, if the X1 rate is changed to 7.3728 MHz all the rates below will double.
Table 7. Data Clock Mux
CCLK maximum rate is 8MHz. Data clock rates will follow exactly the ratio of CCLK to 3.6864MHz.
Table 8. CR - Command Register
CR is used to write commands to the Quad UART.
CR[2] - Lock TxD and RxFIFO enables
If set, the transmitter and receiver enable bits, CR[1:0] are not
significant. The enabled/disabled state of a receiver or transmitter
can be changed only if this bit is at zero during the time of the write
to the command register. WRITES TO THE UPPER BITS OF THE
CR WOULD USUALLY HAVE CR[2] AT 1 to maintain the condition
of the receiver and transmitter. The bit provides a mechanism for
writing commands to a channel, via CR[7:3], without the necessity of
keeping track of or reading the current enable status of the receiver
and transmitter.
CR[1] - Enable Transmitter
A one written to this bit enables operation of the transmitter. The
TxRDY status bit will be asserted. When disabled by writing a zero
to this bit, the command terminates transmitter operation and resets
the TxRDY and TxEMT status bits. However, if a character is being
transmitted or if characters are loaded in the TxFIFO when the
transmitter is disabled, the transmission of the all character(s) is
completed before assuming the inactive state.
CR[0] - Enable Receiver
A one written to this bit enables operation of the receiver. If not in
the special Wake-up mode, this also forces the receiver into the
search for start bit state. If a zero is written, this command
terminates operation of the receiver immediately - a character being
2006 Aug 15
Channel Command codes see
“Command Register Table”
Quad UART for 3.3 V and 5 V supply voltage
Clock Select Code
Bits 4:0
00000
00001
00010
00011
00100
00101
00110
01000
01001
01010
01011
01100
01101
00111
01110
01111
Bits 7:3
Reserved
Bits 7:5
CCLK = 3.6864 MHz
Clock selection,
1 = Hold present condition of Tx & Rx Enables
0 = Change Tx & Rx enable conditions
BRG - 14.4K
BRG - 1200
BRG - 1800
BRG - 2400
BRG - 3600
BRG - 4800
BRG - 7200
BRG - 9600
BRG - 150
BRG - 200
BRG - 300
BRG - 450
BRG - 600
BRG - 900
BRG - 50
BRG - 75
Transmitter/Receiver Clock select code, (see Clock Mux Table below)
Bit 2
20
Clock Select Code
received will be lost. The command has no effect on the receiver
status bits or any other control registers. If the special wake-up
mode is programmed, the receiver operates even if it is disabled
(see Wake-up Mode).
CR[7:3] - Miscellaneous Commands (See Table below)
The encoded value of this field can be used to specify a single
command as follows:
00000
00001
00010
00011
00100
00101
10000
10001
10010
10100
10101
10011
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
No command.
Reserved.
Reset receiver. Resets the receiver as if a hardware reset
had been applied. The receiver is disabled and the FIFO
pointer is reset to the first location effectively discarding all
unread characters in the FIFO.
Reset transmitter. Resets the transmitter as if a hardware
reset had been applied.
Reset error status. Clears the received break, parity error,
framing error, and overrun error bits in the status register
(SR[7:4]). Used in character mode to clear overrun error
status (although RB, PE and FE bits will also be cleared),
and in block mode to clear all error status after a block of
data has been received.
Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2]) to be
cleared to zero.
Bits 4:0
1 = Enable Tx
0 = Disable Tx
Bit 1
I/O2 rcvr, I/O3 xmit -16x
I/O2 rcvr, I/O3 xmit-1x
CCLK = 3.6864 MHz
Clock selection,
BRG - 115.2K
BRG - 230.4K
BRG - 19.2K
BRG - 28.8K
BRG - 38.4K
BRG - 57.6K
BRG C/T 0
BRG C/T 1
Reserved
Reserved
Reserved
Reserved
Gin0
Gin1
1 = Enable Rx
0 = Disable Rx
SC28L194
Product data sheet
Bit 0