PCA9516APW NXP Semiconductors, PCA9516APW Datasheet - Page 6

• Manufacturer Part Number: PCA9516APW
• Description: I/O Expanders, Repeaters & Hubs I2C BUS HUB 5-CH
• Manufacturer: NXP Semiconductors

Specifications of PCA9516APW

• Logic Family: PCA
• Number Of Lines (input / Output): 14 / 10
• Propagation Delay Time: 150 ns
• Operating Supply Voltage: 2.3 V to 3.6 V
• Power Dissipation: 300 mW
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-16
• Logic Type: I2C Hub
• Mounting Style: SMD/SMT
• Number Of Input Lines: 14
• Number Of Output Lines: 10
• Lead Free Status / Rohs Status: Details
• Other names: PCA9516APW,112

NXP Semiconductors
PCA9516A_3
Product data sheet
The PCA9516A is 5.5 V tolerant so it does not require any additional circuitry to translate
between the different bus voltages.
When one side of the PCA9516A is pulled LOW by a device on the I
hysteresis type input detects the falling edge and causes an internal driver on the other
side to turn on, thus causing the other side to also go LOW. The side driven LOW by the
PCA9516A will typically be at V
In order to illustrate what would be seen in a typical application, refer to
Figure
we would see the waveform shown in
transmission until the falling edge of the 8
the data line (SDA) while the slave pulls it LOW through the PCA9516A. Because the V
of the PCA9516A is typically around 0.5 V, a step in the SDA will be seen. After the master
has transmitted the 9
On the Bus 1 side of the PCA9516A, the clock and data lines would have a positive offset
from ground equal to the V
be pulled to the V
It is important to note that any arbitration or clock stretching events on Bus 1 require that
the V
in
transmitted to Bus 0.
Fig 5.
Section 9 “Static
OL
7. If the bus master in
of the devices on Bus 1 be 70 mV below the V
Typical application
MASTER
OL
400 kHz
BUS
characteristics”) to be recognized by the PCA9516A and then
of the slave device that is very close to ground in our example.
th
SDA
SCL
clock pulse, the slave releases the data line.
Rev. 03 — 23 April 2009
OL
3.3 V
Figure 5
of the PCA9516A. After the 8
OL
= 0.5 V.
SDA0
SCL0
EN1
EN2
EN3
EN4
Figure 6
were to write to the slave through the PCA9516A,
PCA9516A
th
V
CC
clock pulse. At that point, the master releases
SDA1
SDA2
SDA3
SDA4
SCL1
SCL2
SCL3
SCL4
on Bus 0. This looks like a normal I
3.3 V or 5 V
OL
3.3 V
5 V
5 V
of the PCA9516A (see V
th
clock pulse, the data line will
SDA
SCL
SDA
SCL
SDA
SCL
5-channel I
SLAVE 1
SLAVE 2
SLAVE 3
400 kHz
400 kHz
100 kHz
PCA9516A
002aae617
2
C-bus, a CMOS
© NXP B.V. 2009. All rights reserved.
Figure 6
2
C-bus hub
and
OL
2
C-bus
6 of 19
V
OL
ILc