TUA4401KV3.0 Infineon Technologies, TUA4401KV3.0 Datasheet - Page 41
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TUA4401KV3.0
Manufacturer Part Number
TUA4401KV3.0
Description
Manufacturer
Infineon Technologies
Datasheet
1.TUA4401KV3.0.pdf
(41 pages)
Specifications of TUA4401KV3.0
Lead Free Status / Rohs Status
Not Compliant
Wireless Components
Table 5-4
Parameter
LOW level input voltage (SDA, SCL)
HIGH level input voltage (SDA, SCL)
Pulse width of spikes which must be suppressed by the input fil-
ter
LOW level output voltage 3mA sink current (SDA)
Output fall time from V
from 10pF to 400pFwith up to 3mA
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set -up time
Rise, fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
IHmin
to V
2)
Note that the maximum t
longer than the specified maximum t
allows series protection resistors to be connected between the SDA / SCL pins
and the SDA /SCL bus lines without exceeding the maximum specified t
C
ILmax
b
= capacitance of one bus line in pF.
with a bus capacitance
5 - 14
F
for the SDA and SCL bus lines quoted at 300ns is
Symbol
V
V
t
V
t
f
t
t
t
t
t
t
t
t
t
C
SP
OF
SCL
BUF
HO.STA
LOW
HIGH
SU.STA
HD.DAT
SU.DAT
R
SU.STO
IL
IH
OL
b
, t
OF
F
for the output stages (250ns).This
20+0.1C
20+0.1C
2.10
min
-0.5
100
1.3
0.6
1.3
0.6
0.6
0.6
0
0
0
0
b
b
2)
2)
Specification, 17.02.00
max
0.90
5.50
0.40
250
400
300
400
50
TUA 4401K
Reference
F
Unit
kHz
pF
.
ns
ns
µs
µs
µs
µs
µs
ns
ns
ns
µs
V
V
V