TUA4401KV3.0 Infineon Technologies, TUA4401KV3.0 Datasheet - Page 23

• Manufacturer Part Number: TUA4401KV3.0
• Manufacturer: Infineon Technologies

Specifications of TUA4401KV3.0

• Lead Free Status / Rohs Status: Not Compliant

Wireless Components
7. Crystal oscillator
8. Output ports
9. I
+/- (12.5 kHz...200 kHz) for D7=1 in subaddress 05H. The results IF_CENT
and IF_WINDOW are read out via bus (read-subaddress 82H&83H) or pin
Station_Detect.
If the IF frequency is into the preselected window, Station_Detect goes from
high to low level. If the IF frequency is outside the preselected window,
Station_Detect is high. The bit IF_WINDOW is a hint IF-frequency that is to
low (IF_WINDOW=high) or is to high (IF_WINDOW=low).
In addition to the frequency measurement, thresholds for multipath and field-
strength voltages can be programmed via bus (subaddress 0BH).
Station_Detect will only go to low level in case of field-strength and multipath
voltages are beyond the thresholds and the frequency is inside the window.
When setting the thresholds to zero multipath and fieldstrength evaluation is
disabled.
A master crystal oscillator provides all necessary clock frequencies for the
whole IC. A 61.5 MHz crystal is used in 3rd harmonic mode.
The oscillator frequency can fine tuned with a serial bus controlled 4 bit D/A
converter.
The crystal frequency is used as reference frequency for the PLL oscillator
and IF counter. It is also used as clock for the ADC’s. Finally the crystal fre-
quency divided by 6 (10.25 MHz) is available at a pin as low pass filtered
voltage, it can be disabled with the serial bus.
PORT_1 / 2 are NMOS Open drain outputs.
The TUA4401K supports the I
SDA) are Schmitt triggered input buffer for 3V or 5V C.
The bit stream begins with the most significant bit (MSB), is shifted in (write
mode) on the low to high transition of CLK and is shifted out (read mode) on
the high to low transition of CLK
I
Data Transition:
Data transition on the pin SDA must only occur when the clock SCL is low.
SDA transitions while SCL is high will be interpreted as start or stop condi-
tion.
Start Condition (STA):
A start condition is defined by a high to low transition of the SDA line while
SCL is at a stable high level.This start condition must precede any command
and initiate a data transfer onto the bus.
Stop Condition (STO):
A stop condition is defined by a low to high transition of the SDA while the
SCL line is at a stable high level. This condition terminate the communication
between the devices and forces the bus interface into the initial conditions.
2
2
C Bus
C bus mode:
3 - 15
2
C bus protocol (2 wire). All bus pins ( SCL,
Functional Description
Specification, 17.02.00
TUA 4401K