TDA5231XT Infineon Technologies, TDA5231XT Datasheet - Page 107
TDA5231XT
Manufacturer Part Number
TDA5231XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.TDA5231XT.pdf
(186 pages)
Specifications of TDA5231XT
Operating Temperature (min)
-40C
Operating Temperature (max)
105C
Operating Temperature Classification
Industrial
Product Depth (mm)
4.4mm
Product Length (mm)
9.7mm
Lead Free Status / Rohs Status
Compliant
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ADDR:
Dual:
ADDR:
Dual:
ADDR:
Data Sheet
1:0
4:0
4:0
Bit R/W Description
Bit R/W Description
Bit R/W Description
2
W
W
ATSILENA
W
ATSILENB
W
0x82
0x83
0x84
MANCPAJ: Manchester code phase readjustment
0: disabled - Manchester code polarity is defined by the TSI pattern.
1: enabled - the code phase readjustment will be done with each “1001” or
“0110” manchester data change.
TSIDETMOD: TSI Detection Mode
00b: 16-Bit Mode - TSI configuration A AND B valid (sequentially), B is valid
if the ATSILENB>0
01b: 8-Bit Mode - TSI configurations A OR B (parallel)
10b: 8-Bit Gap Mode- TSI configurations A AND B with Gap (sequentially
with Gap between TSIA & TSIB)
11b: 8-Bit extended Mode - TSI configurations A OR B (parallel with
matching information), synchronization will be done on full TSI length,
dependent on found TSI A or B, 1 or 0 will be send as 1st received bit.
TSI A Length (in chips):
(0x11 up to 0x1F not used)
Min: 00h = 0 Bit; works only in 16-Bit Mode: FSYNC will be generated after
Symbol Synchronization. In other modes, the smallest possible value to
generate a FSYNC will be 01h. Be aware that such small values makes it
impossible to find the right phase of the pattern in the data stream and
therefore incorrect data and code violations can be generated.
Max: 10h = 16 Chips = 8 Bit
TSI B Length (in chips):
(0x11 up to 0x1F not used)
Min: 00h =0 Bit (see also ATSILENA)
Max: 10h = 16 Chips = 8 Bit
and
and
and
0xA2
0xA3
0xA4
and BTSILENA:
and BTSILENB:
TSI A Length
TSI B Length
103
Functional Description
Reset Value: 0x00
Reset Value: 0x00
Reset Value: 0x00
Version 4.0, 2007-06-01
TDA523x
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