ISP1761BE STEricsson, ISP1761BE Datasheet - Page 44

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 33.
Table 34.
ISP1761_5
Product data sheet
Bit
31 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
ATL_PTD_LAST_
PTD[31:0]
ATL PTD Last PTD register (address 0158h) bit description
HW Mode Control - Hardware Mode Control register (address 0300h) bit allocation
8.2.15 ATL PTD Last PTD register
ANA_DIGI_
ALL_ATX_
reserved
8.3.1 HW Mode Control register
RESET
R/W
R/W
R/W
8.3 Configuration registers
R/W
31
23
OC
15
0
0
7
0
0
When a bit in the PTD Skip map is set to logic 1 that PTD will be skipped although its V bit
may be set. The information in that PTD is not processed. For example, NextPTDPointer
will not affect the order of processing of PTDs. The Skip bit should not normally be set on
the position indicated by NextPTDPointer.
The bit description of the ATL PTD Last PTD register is given in
Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed
(checking V = 1) in that PTD category. Subsequently, the process will restart with the first
PTD of that group. This is useful to reduce the time in which all the PTDs, the respective
memory space, would be checked, especially if only a few PTDs are defined. The
LastPTD bit must normally be set to a higher position than any other position indicated by
the NextPTDPointer from an active PTD.
Table 34
DACK_
Access
R/W
POL
R/W
R/W
R/W
R/W
30
22
14
0
0
6
0
0
shows the bit allocation of the register.
reserved
Value
0000 0000h
DREQ_
R/W
R/W
POL
R/W
R/W
29
21
13
0
0
5
0
0
Rev. 05 — 13 March 2008
[1]
Description
ATL PTD Last PTD: Last PTD of the 32 PTDs.
1h — One PTD in ATL
2h — Two PTDs in ATL
4h — Three PTDs in ATL
R/W
R/W
R/W
R/W
12
28
20
0
0
0
4
0
reserved
reserved
DEV_DMA
reserved
R/W
[1]
[1]
11
R/W
R/W
R/W
0
27
19
0
0
3
0
[1]
COMN_IRQ
INTR_POL
R/W
10
R/W
R/W
R/W
0
26
18
0
0
2
0
Hi-Speed USB OTG controller
Table
COMN_
LEVEL
INTR_
DMA
R/W
R/W
R/W
R/W
25
17
9
0
33.
0
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1761
DATA_BUS
GLOBAL_
INTR_EN
_WIDTH
R/W
R/W
R/W
R/W
43 of 163
24
16
0
0
8
1
0
0