ISP1761BE STEricsson, ISP1761BE Datasheet - Page 111

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 109. Endpoint Index register (address 022Ch) bit allocation
[1]
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
10.6.2 Control Function register
R/W
7
0
0
reserved
For example, to access the OUT data buffer of endpoint 1 using the Data Port register, the
Endpoint Index register must be written first with 02h.
Remark: The Endpoint Index register and the DMA Endpoint register must not point to the
same endpoint, irrespective of IN and OUT.
Table 110. Endpoint Index register (address 022Ch) bit description
Table 111. Addressing of endpoint buffers
The Control Function register performs the buffer management on endpoints. It consists
of 1 byte, and the bit configuration is given in
validate any enabled data endpoint. Before accessing this register, the Endpoint Index
register must first be written to specify the target endpoint.
Bit
7 to 6
5
4 to 1
0
Buffer name
SETUP
Control OUT
Control IN
Data OUT
Data IN
•
•
Endpoint MaxPacketSize
Endpoint Type
[1]
R/W
6
0
0
Symbol
-
EP0SETUP
ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access of buffer
DIR
EP0SETUP
R/W
5
1
1
EP0SETUP
1
0
0
0
0
Rev. 05 — 13 March 2008
Description
reserved
Endpoint 0 Set up: Selects the SETUP buffer for endpoint 0.
0 — Data buffer
1 — SETUP buffer
Must be logic 0 for access to endpoints other than set-up token buffer.
length, buffer status, control function, data port, endpoint type and
MaxPacketSize.
Direction bit: Sets the target endpoint as IN or OUT.
0 — Target endpoint refers to OUT (RX) FIFO
1 — Target endpoint refers to IN (TX) FIFO
R/W
4
0
0
R/W
Table
3
0
0
ENDPIDX
00h
00h
00h
0Xh
0Xh
ENDPIDX[3:0]
112. The register bits can stall, clear or
R/W
2
0
0
Hi-Speed USB OTG controller
DIR
0
0
1
0
1
R/W
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
110 of 163
R/W
DIR
0
0
0