GS880Z36BT-250 GSI TECHNOLOGY, GS880Z36BT-250 Datasheet - Page 12

• Manufacturer Part Number: GS880Z36BT-250
• Manufacturer: GSI TECHNOLOGY

Specifications of GS880Z36BT-250

• Density: 9Mb
• Access Time (max): 5.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 181.8MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 160mA
• Operating Supply Voltage (min): 2.3/3V
• Operating Supply Voltage (max): 2.7/3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.04b 11/2010
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
3rd address
4th address
1st address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0]
00
01
10
11
A[1:0]
01
10
11
00
A[1:0]
10
00
01
11
A[1:0]
Pin Name
11
00
01
10
12/24
LBO
FT
ZZ
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
H or NC
L or NC
2nd address
State
3rd address
1st address
4th address
H
H
L
L
GS880Z18/32/36BT-333/300/250/200/150
A[1:0]
00
01
10
11
Standby, I
Interleaved Burst
Flow Through
A[1:0]
Linear Burst
Function
Pipeline
01
00
10
11
Active
DD
© 2001, GSI Technology
= I
A[1:0]
SB
10
00
01
11
A[1:0]
11
10
01
00