DSPA56371AF150B Freescale Semiconductor, DSPA56371AF150B Datasheet - Page 3

• Manufacturer Part Number: DSPA56371AF150B
• Manufacturer: Freescale Semiconductor

Specifications of DSPA56371AF150B

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Program Memory Size: 192KB
• Operating Supply Voltage (typ): 1.25/3.3V
• Operating Supply Voltage (min): 1.2/3.14V
• Operating Temp Range: -40C to 115C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

The DSP56300 core family offers a new level of performance in speed and power, provided by its rich
instruction set and low power dissipation, thus enabling a new generation of wireless, telecommunications
and multimedia products. For a description of the DSP56300 core, see
Functional
shifter, 24-bit addressing, an instruction patch module and direct memory access (DMA).
The DSP56300 core family members contain the DSP56300 core and additional modules. The modules
are chosen from a library of standard pre-designed elements such as memories and peripherals. New
modules may be added to the library to meet customer specifications. A standard interface between the
DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and
peripheral configurations. Refer to
Core features are described fully in the DSP56300 Family Manual. Pinout, memory and peripheral
features are described in this manual.
Freescale Semiconductor
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DSP56300 modular chassis
— 181 Million Instructions Per Second (MIPS) with a 181 MHz clock at an internal logic supply
— Object Code Compatible with the 56K core
— Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit
— Program Control with position independent code support and instruction patch support
— EFCOP running concurrently with the core, capable of executing 181 million filter taps per
— Six-channel DMA controller
— Low jitter, PLL based clocking with a wide range of frequency multiplications (1 to 255),
— Internal address tracing support and OnCE for Hardware/Software debugging
— JTAG port
— Very low-power CMOS design, fully static design with operating frequencies down to DC
— STOP and WAIT low-power standby modes
On-chip Memory Configuration
— 48Kx24 Bit Y-Data RAM and 32Kx24 Bit Y-Data ROM
— 36Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM
— 64Kx24 Bit Program and Bootstrap ROM
— 4Kx24 Bit Program RAM.
— PROM patching mechanism
— Up to 32Kx24 Bit from Y Data RAM and 8Kx24 Bit from X Data RAM can be switched to
Peripheral modules
— Enhanced Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or
(QVDDL) of 1.25 V
arithmetic support
second at peak performance
predivider factors (1 to 31) and power saving clock divider (2
Program RAM resulting in up to 44Kx24 Bit of Program RAM.
Blocks. Significant architectural enhancements to the DSP56300 core family include a barrel
DSP56371 User’s Manual, Memory Configuration
DSP56371 Data Sheet, Rev. 4.1
Section 2.4 DSP56300 Core
i
: i=0 to 7). Reduces clock noise.
section.
DSP56371 Overview
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