DSPA56371AF150B Freescale Semiconductor, DSPA56371AF150B Datasheet - Page 18

• Manufacturer Part Number: DSPA56371AF150B
• Manufacturer: Freescale Semiconductor

Specifications of DSPA56371AF150B

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Program Memory Size: 192KB
• Operating Supply Voltage (typ): 1.25/3.3V
• Operating Supply Voltage (min): 1.2/3.14V
• Operating Temp Range: -40C to 115C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

Signal/Connection Descriptions
18
Signal
HREQ
Name
MOSI
HA2
HA0
SS
Signal Type
Input or
Input or
Output
output
Input
Input
Input
Tri-stated SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the
Tri-stated SPI Slave Select—This signal is an active low Schmitt-trigger input when
Tri-stated Host Request—This signal is an active low Schmitt-trigger input when
during
Reset
State
Table 7. Serial Host Interface Signals (continued)
master data output line. The MOSI signal is used in conjunction with the MISO
signal for transmitting and receiving serial data. MOSI is the slave data input line
when the SPI is configured as a slave. This signal is a Schmitt-trigger input when
configured for the SPI Slave mode.
I
for the I
form the slave device address. HA0 is ignored when configured for the I
mode.
This signal is tri-stated during hardware, software and individual reset. Thus,
there is no need for an external pull-up in this state.
Internal Pull up resistor.
This input is 5 V tolerant.
configured for the SPI mode. When configured for the SPI Slave mode, this signal
is used to enable the SPI slave for transfer. When configured for the SPI master
mode, this signal should be kept deasserted (pulled high). If it is asserted while
configured as SPI master, a bus error condition is flagged. If SS is deasserted,
the SHI ignores SCK clocks and keeps the MISO output signal in the
high-impedance state.
I
for the I
to form the slave device address. HA2 is ignored in the I
This signal is tri-stated during hardware, software and individual reset. Thus,
there is no need for an external pull-up in this state.
Internal Pull up resistor.
This input is 5 V tolerant.
configured for the master mode but an active low output when configured for the
slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the SHI
is ready for the next data word transfer and deasserted at the first clock pulse of
the new data word transfer. When configured for the master mode, HREQ is an
input. When asserted by the external slave device, it will trigger the start of the
data word transfer by the master. After finishing the data word transfer, the master
will await the next assertion of HREQ to proceed to the next transfer.
This signal is tri-stated during hardware, software, personal reset, or when the
HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for an external
pull-up in this state.
Internal Pull up resistor.
This input is 5 V tolerant.
2
2
C Slave Address 0—This signal uses a Schmitt-trigger input when configured
C Slave Address 2—This signal uses a Schmitt-trigger input when configured
DSP56371 Data Sheet, Rev. 4.1
2
2
C mode. When configured for the I
C mode. When configured for I
Signal Description
2
C slave mode, the HA0 signal is used to
2
C Slave mode, the HA2 signal is used
2
C master mode.
Freescale Semiconductor
2
C master