IS42S32200B-6T ISSI, Integrated Silicon Solution Inc, IS42S32200B-6T Datasheet - Page 29

• Manufacturer Part Number: IS42S32200B-6T
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32200B-6T

• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 6ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 185mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

IS42S32200B
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
Integrated Silicon Solution, Inc. — www.issi.com —
R e v . 0 0 C
09/29/03
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic 1.
In this mode, all WRITE commands result in the access of a
single column location (burst of one), regardless of the
programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
Internal States
Internal States
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
DQM
CLK
CLK
DQ
DQ
Read - AP
T0
Page Active
T0
BANK n
BANK n,
NOP
COL a
Page Active
CAS Latency - 3 (BANK n)
READ - AP
BANK n,
T1
BANK n
T1
NOP
COL a
Page Active
Page Active
READ with Burst of 4
READ with Burst of 4
CAS Latency - 3 (BANK n)
T2
T2
NOP
NOP
READ - AP
BANK m
BANK m,
T3
T3
NOP
COL b
D
OUT
1-800-379-4774
a
CAS Latency - 3 (BANK m)
SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
2. Interrupted by a WRITE (with or without auto precharge):
Interrupt Burst, Precharge
A READ to bank m will interrupt a READ on bank n, CAS
latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered.
A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used two clocks prior
to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
WRITE - AP
BANK m,
BANK m
COL b
T4
T4
NOP
D
D
IN
t
OUT
RP - BANK n
READ with Burst of 4
b
a
Interrupt Burst, Precharge
WRITE with Burst of 4
T5
T5
D
NOP
NOP
D
IN
OUT
t
RP - BANK n
b+1
a+1
T6
T6
D
NOP
NOP
D
IN
OUT
b+2
b
DON'T CARE
DON'T CARE
Idle
T7
T7
D
NOP
D
NOP
IN
Write-Back
Precharge
OUT
b+3
t
t
RP - BANK m
RP - BANK m
b+1
Idle
ISSI
29
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