LP2995LQ National Semiconductor, LP2995LQ Datasheet - Page 6

• Manufacturer Part Number: LP2995LQ
• Manufacturer: National Semiconductor

Specifications of LP2995LQ

• Voltage Regulator Type: Linear
• Topology: LDO
• Number Of Outputs: Single
• Input Voltage (min): 2.2V
• Input Voltage (max): 5.5V
• Package Type: LLP EP
• Output Current: 1.5A
• Load Regulation: 0.5%
• Operating Temp Range: 0C to 125C
• Operating Temperature Classification: Commercial
• Pin Count: 16
• Mounting: Surface Mount
• Quiescent Current (max): 400uA
• Lead Free Status / Rohs Status: Not Compliant

www.national.com
Block Diagram
Description
The LP2995 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2 and SSTL-3. The
LP2995 is capable of sinking and sourcing current at the out-
put V
reference voltage that also tracks VDDQ / 2 is generated on
the V
SDRAM and Northbridge Chipset. V
V
range while preventing shoot through on the output stage.
Series Stub Termination Logic (SSTL) was created to im-
prove signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent
data error from signal reflections while transmitting at high
frequencies encountered with DDR RAM. The most common
form of termination is Class II single parallel termination. This
involves using one Rs series resistor from the chipset to the
memory and one Rt termination resistor. This implementation
can be seen below in
REF
TT
REF
voltage with a tight tolerance over the entire current
, regulating the voltage to equal VDDQ / 2. A buffered
pin for providing a global reference to the DDR-
Figure
1.
TT
is designed to track the
6
Typical values for R
be changed to scale the current requirements from the
LP2995. For determination of the current requirements of
DDR-SDRAM termination please refer to the accompanying
application notes.
S
and R
FIGURE 1.
T
are 25 Ohms although these can
20039308
20039301