LP2995LQ National Semiconductor, LP2995LQ Datasheet - Page 10

LP2995LQ

Manufacturer Part Number
LP2995LQ
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of LP2995LQ

Voltage Regulator Type
Linear
Topology
LDO
Number Of Outputs
Single
Input Voltage (min)
2.2V
Input Voltage (max)
5.5V
Package Type
LLP EP
Output Current
1.5A
Load Regulation
0.5%
Operating Temp Range
0C to 125C
Operating Temperature Classification
Commercial
Pin Count
16
Mounting
Surface Mount
Quiescent Current (max)
400uA
Lead Free Status / Rohs Status
Not Compliant

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PCB Layout Considerations
1.
2.
3.
AVIN and PVIN should be tied together for optimal
performance. A local bypass capacitor should be placed
as close as possible to the PVIN pin.
GND should be connected to a ground plane with
multiple vias for improved thermal performance.
V
at the point where regulation is required. For
SENSE
should be connected to the V
TT
termination bus
10
4.
5.
motherboard applications an ideal location would be at
the center of the termination bus.
VDDQ can be connected remotely to the VDDQ rail input
at either the DIMM or the Chipset. This provides the most
accurate point for creating the reference voltage.
V
ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the
V
REF
REF
should be bypassed with a 0.01 µF or 0.1 µF
pin.

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