AM486DX5-133W16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133W16BHC Datasheet - Page 47

• Manufacturer Part Number: AM486DX5-133W16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133W16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.45V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

The SMBASE must be a 32-Kbyte aligned, 32-bit integer
that indicates a base address for the SMRAM context
save area and the SMI jump vector. For example, when
the processor first powers up, the range for the SMRAM
area is from 38000h–3FFFFh. The default value for SM-
BASE is 30000h.
As illustrated in Figure 31, the starting address of the
jump vector is calculated by:
SMBASE + 8000h
The starting address for the SMRAM state save area is
calculated by:
SMBASE + [8000h + 7FFFh]
When this feature is enabled, the SMRAM register map
is addressed according to the above formula.
To change the SMRAM base address and SMI jump
vector location, SMI handler modifies the SMBASE slot.
Upon executing an RSM instruction, the processor
reads the SMBASE slot and stores it internally. Upon
recognition of the next SMI request, the processor uses
the new SMBASE slot for the SMRAM dump and SMI
jump vector. If the modified SMBASE slot does not con-
tain a 32-Kbyte aligned value, the RSM microcode caus-
es the CPU to enter the shutdown state.
6.8
6.8.1 SMRAM Interface
The hardware designed to control the SMRAM space
must follow these guidelines:
SMBASE + 8000h
SMBASE + 8000h
Initialize SMRAM space during system boot up. Ini-
tialization must occur before the first SMI occurs.
Initialization of SMRAM space must include installa-
tion of an SMI handler and may include installation
of related data structures necessary for particular
SMM applications. The memory controller interfac-
ing SMRAM should provide a means for the initial-
ization code to open the SMRAM space manually.
The memory controller must decode a minimum ini-
tial SMRAM address space of 38000h–3FFFFh.
SMM System Design Considerations
SMBASE
+ 7FFFh
Figure 31. SRAM Usage
Start of State Save
SMI Handler Entry Point
SMRAM
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
The recommended configuration is to use a separate
(non-overlaid) physical address for SMRAM. This non-
overlaid scheme prevents the CPU from improperly ac-
cessing the SMRAM or system RAM directly or through
the cache. Figure 33 shows the relative SMM timing for
non-overlaid SMRAM for systems configured in Write-
through mode. For systems configured in Write-back
mode, WB/WT must be driven Low (as shown in Figure
34) to force caching during SMM to be write-through.
Alternately, caching can be disabled during SMM by
deasserting KEN with SMI (as shown in Figure 35).
When the default SMRAM location is used, however,
SMRAM is overlaid with system main memory (at
38000h–3FFFFh). For simplicity, system designers may
want to use this default address, or they may select
another overlaid address range. However, in this case
the system control circuitry must use SMIACT to distin-
guish between SMRAM and main system memory, and
must restrict SMRAM space access to the CPU only.
To maintain cache coherency and to ensure proper
system operation in systems configured in Write-
through mode, the system must flush both the CPU inter-
nal cache and any second-level caches in response to
SMIACT going Low. A system that uses cache during
SMM must flush the cache a second time in response
to SMIACT going High (see Figure 36). If KEN is driven
High when FLUSH is asserted, the cache is disabled
and a second flush is not required (see Figure 37). If the
system is configured in Write-back mode, the cache
must be flushed when SMI is asserted and then disabled
(see Figure 38).
Alternate bus masters (such as DMA controllers)
must not be able to access SMRAM space. The sys-
tem should allow only the CPU, either through SMI
or during initialization, to access SMRAM.
To implement a 0-V suspend function, the system
must have access to all normal system memory from
within an SMI handler routine. If the SMRAM over-
lays normal system memory (see Figure 32), there
must be a method to access overlaid system mem-
ory independently.
(no need to flush
Non-overlaid
SMRAM
memory
caches)
Normal
Figure 32. SMRAM Location
(caches must
be flushed)
Overlaid
memory
memory
Normal
Normal
Overlaid region
SMRAM
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