AM486DX5-133W16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133W16BHC Datasheet - Page 16

• Manufacturer Part Number: AM486DX5-133W16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133W16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.45V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

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first clock. RDY is active during address hold. Data can
be returned to the processor while AHOLD is active.
RDY is active Low and does not have an internal pull-
up resistor. RDY must satisfy setup and hold times t
and t
SMI
SMM Interrupt (Active Low; Input)
A Low signal on the SMI pin signals the processor to
enter System Management mode (SMM). SMI is the
highest level processor interrupt. The SMI signal is rec-
ognized on an instruction boundary, similar to the NMI
and INTR signals. SMI is sampled on every rising clock
edge. SMI is a falling-edge sensitive input. The SMI input
has an internal pull-up resister. Recognition of SMI is
guaranteed in a specific clock if it is asserted synchro-
nously and meets the setup and hold times. If SMI is
asserted asynchronously, it must go High for a minimum
of two clocks before going Low, and it must remain Low
for at least two clocks to guarantee recognition. When
the CPU recognizes SMI, it enters SMM before execut-
ing the next instruction and saves internal registers in
SMM space.
SMIACT
SMM Interrupt Active (Active Low; Output)
SMIACT goes Low in response to SMI. It indicates that
the processor is operating under SMM control. SMIACT
remains Low until the processor receives a RESET sig-
nal or executes the Resume Instruction (RSM) to leave
SMM. This signal is always driven. It does not float dur-
ing bus HOLD or BOFF.
Note: Do not use SRESET to exit from SMM. The sys-
tem should block SRESET during SMM.
SRESET
Soft Reset (Active High; Input)
The CPU samples SRESET on every rising clock edge.
If SRESET is sampled active, the SRESET sequence
begins on the next instruction boundary. SRESET
resets the processor, but, unlike RESET, does not cause
it to sample UP or WB/WT, or affect the FPU, cache, CD
and NW bits in CR0, and SMBASE. SRESET is asyn-
chronous and must meet the same timing as RESET.
The SRESET input has an internal pull-down resistor.
STPCLK
Stop Clock (Active Low; Input)
A Low input signal indicates a request has been made
to turn off the CLK input. When the CPU recognizes a
STPCLK, the processor:
Stops execution on the next instruction boundary
(unless superseded by a higher priority interrupt)
Empties all internal pipelines and write buffers
Generates a Stop Grant acknowledge bus cycle
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for proper chip operation.
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
16
STPCLK is active Low and has an internal pull-up re-
sistor. STPCLK is asynchronous, but it must meet setup
and hold times t
specific clock. STPCLK must remain active until the Stop
Clock special bus cycle is issued and the system returns
either RDY or BRDY.
TCK
Test Clock (Input)
Test Clock provides the clocking function for the JTAG
boundary scan feature. TCK clocks state information
and data into the component on the rising edge of TCK
on TMS and TDI, respectively. Data is clocked out of
the component on the falling edge of TCK on TDO. TCK
uses an internal weak pull-up.
TDI
Test Data Input (Input)
TDI is the serial input that shifts JTAG instructions and
data into the tested component. TDI is sampled on the
rising edge of TCK during the SHIFT-IR and the
SHIFT-DR TAP (Test Access Port) controller states.
During all other TAP controller states, TDI is ignored.
TDI uses an internal weak pull-up.
TDO
Test Data Output (Active High; Output)
TDO is the serial output that shifts JTAG instructions
and data out of the component. TDO is driven on the
falling edge of TCK during the SHIFT-IR and SHIFT-DR
TAP controller states. Otherwise, TDO is three-stated.
TMS
Test Mode Select (Active High; Input)
TMS is decoded by the JTAG TAP to select the operation
of the test logic. TMS is sampled on the rising edge of
TCK. To guarantee deterministic behavior of the TAP
controller, the TMS pin has an internal pull-up resistor.
UP
Write/Read (Input)
The processor samples the Upgrade Present (UP) pin
in the clock before the falling edge of RESET. If it is Low,
the processor three-states its outputs immediately. UP
must remain asserted to keep the processor inactive.
The pin uses an internal pull-up resistor.
VOLDET—(168-Pin PGA Package Only)
Voltage Detect (Output)
VOLDET provides an external signal to allow the system
to determine the CPU input power level (3 V or 5 V). For
the Enhanced Am486DX microprocessors, the pin ties
internally to V
SS
20
.
and t
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to ensure recognition in any