AM486DX5-133W16BHC AMD (ADVANCED MICRO DEVICES), AM486DX5-133W16BHC Datasheet - Page 30

• Manufacturer Part Number: AM486DX5-133W16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX5-133W16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 133MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.45V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

30
Step 4 In the same clock cycle, a snoop request to the
Step 5 Two clock cycles after EADS asserts, HITM be-
Step 6 Because the processor-initiated access cannot
Step 7 During the write-back sequence, AHOLD is
Step 8 The write-back access is finished when BLAST
Step 9 After the last write-back access, the BIU starts
Step 10 In the same clock cycle, the snooping cache
Step 11 The write of data A is finished if BRDY transi-
The software write sequence was first data A and then
data B. But on the external bus the data appear first as
HITM
ADS
BLAST
BRDY
Note:
The circled numbers in this figure represent the steps in section 4.8.7.1.
CLK
Write Buffer
Cached Data
AHOLD
EADS
Data
same address where data B resides is started
because EADS = 0. The snoop hits a modified
line. EADS is ignored due to the hit of a modified
line, but is detected again as early as in step 10.
comes valid.
be finished (AHOLD is still 1), the BIU gives
priority to a write-back access that does not re-
quire the use of the address bus. Therefore, in
the clock cycle, the cache starts the write-back
sequence indicated by ADS = 0 and W/R = 0.
deasserted.
and BRDY transition to 0.
writing data A from the write buffers. This is
indicated by ADS = 0 and W/R = 0.
drives HITM back to 1.
tions to 0 (BLAST = 0), because it is a single
word.
B original
XXX
1
Figure 14. Write Cycle Reordering Due to Buffering
2
A
Enhanced Am486DX Microprocessor Family
3
B modified
4
P R E L I M I N A R Y
5
6
data B and then data A. The order of writes is changed.
In most cases, it is unnecessary to strictly maintain the
ordering of writes. However, some cases (for example,
writing to hardware control registers) require writes to
be observed externally in the same order as pro-
grammed. There are two options to ensure serialization
of writes, both of which drive the cache to Write-through
mode:
1. Set the PWT bit in the page table entries.
2. Drive the WB/WT signal Low when accessing these
Option 1 is an operating-system-level solution not di-
rectly implemented by user-level code. Option 2, the
hardware solution, is implemented at the system level.
3.8.7.2
The use of BOFF to perform snooping of the on-chip
cache is used in systems where more than one cache-
able bus master resides on the microprocessor bus. The
BOFF signal forces the microprocessor to relinquish the
bus in the following clock cycle, regardless of the type
of bus cycle it was performing at the time. Consequently,
the use of BOFF as a bus arbitrator should be imple-
mented with care to avoid system problems.
3.8.8 BOFF Design Considerations
The use of BOFF as a bus arbitration control mechanism
is immediate. BOFF forces the microprocessor to abort
an access in the following clock cycle after it is asserted.
The following design issues must be considered.
memory locations.
B
Ignored
BOFF Write-Back Arbitration
Implementation
B+4
7
B+8
B+12
8
10
9
A
11