PCF8578H NXP Semiconductors, PCF8578H Datasheet - Page 24

• Manufacturer Part Number: PCF8578H
• Manufacturer: NXP Semiconductors

Specifications of PCF8578H

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: LQFP
• Pin Count: 64
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 6V
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
9
The I
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL) which
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
9.1
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this moment will be interpreted as control signals.
9.2
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH, is defined as the STOP condition (P).
9.3
A device transmitting a message is a 'transmitter', a device
receiving a message is the 'receiver'. The device that
controls the message flow is the 'master' and the devices
which are controlled by the master are the 'slaves'.
2003 Apr 14
LCD row/column driver for
dot matrix graphic displays
CHARACTERISTICS OF THE I
2
C-bus is for bidirectional, two-line communication
Bit transfer
Start and stop conditions
System configuration
SDA
SCL
2
C-BUS
Fig.15 Bit transfer.
data valid
data line
stable;
24
9.4
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down
the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal the end of a data transmission to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
allowed
change
of data
Acknowledge
MBA607
Product specification
PCF8578