UPD78F0034AGK-9ET Renesas Electronics America, UPD78F0034AGK-9ET Datasheet - Page 35

• Manufacturer Part Number: UPD78F0034AGK-9ET
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034AGK-9ET

• Lead Free Status / Rohs Status: Supplier Unconfirmed

ASTB high-level width
Address setup time
Address hold time
Input time from address to data
Output time from RD↓ to address
Input time from RD↓ to data
Read data hold time
RD low-level width
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
WAIT low-level width
Write data setup time
Write data hold time
WR low-level width
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
Delay time from RD↑ to ASTB↑ in
external fetch
Hold time from RD↑ to address in
external fetch
Write data output time from RD↑
Write data output time from WR↓
Hold time from WR↑ to address
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
(2) Read/write operation (T
Remarks 1. t
Parameter
2. n indicates the number of waits.
3. C
pins.)
CY
L
= 100 pF (C
= T
CY
/4
L
A
is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
= –40 to +85
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WRADH
t
t
t
t
t
t
t
RDWT1
RDWT2
ASTRD
ASTWR
RDAST
RDADH
WRWT
t
t
WRWD
WTWR
t
t
t
t
RDWD
WTRD
ASTH
ADD1
ADD2
RDAD
RDD1
RDD2
WRL1
RDL1
RDL2
RDH
WDS
WDH
ADS
ADH
WTL
Data Sheet U14040EJ4V0DS
°
C, V
Conditions
DD
= 1.8 to 2.7 V)
(1.5 + 2n)t
(2.5 + 2n)t
(0.5 + 2n)t
(1.5 + 2n)t
0.8t
0.8t
0.8t
2t
µ PD78F0034A, 78F0034AY
0.3t
0.5t
0.5t
CY
MIN.
120
CY
CY
CY
20
60
20
20
40
40
0
0
– 60
CY
– 60
– 60
– 60
CY
CY
CY
CY
CY
CY
– 92
– 92
+ 10
– 60
(2 + 2n)t
(3 + 2n)t
(2 + 2n)t
(3 + 2n)t
1.2t
1.2t
2.5t
2.5t
(2 + 2n)t
t
t
t
CY
CY
CY
MAX.
1.2t
CY
CY
CY
CY
400
240
– 350
– 132
– 100
CY
CY
CY
CY
+ 120
+ 120
+ 100
+ 100
CY
– 233
– 240
– 325
– 332
CY
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3/3)
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