UPD78F0034AGK-9ET Renesas Electronics America, UPD78F0034AGK-9ET Datasheet - Page 33

• Manufacturer Part Number: UPD78F0034AGK-9ET
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034AGK-9ET

• Lead Free Status / Rohs Status: Supplier Unconfirmed

ASTB high-level width
Address setup time
Address hold time
Input time from address to data
Output time from RD↓ to address
Input time from RD↓ to data
Read data hold time
RD low-level width
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
WAIT low-level width
Write data setup time
Write data hold time
WR low-level width
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
Delay time from RD↑ to ASTB↑ in
external fetch
Hold time from RD↑ to address in
external fetch
Write data output time from RD↑
Write data output time from WR↓
Hold time from WR↑ to address
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
(2) Read/write operation (T
Remarks 1. t
Parameter
2. n indicates the number of waits.
3. C
pins.)
CY
L
= 100 pF (C
= T
CY
/4
A
L
is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
= –40 to +85
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RDWT1
RDWT2
t
ASTWR
RDADH
WRADH
t
t
ASTRD
RDAST
WRWD
t
WRWT
t
t
RDWD
WTWR
t
t
RDAD
t
WTRD
ASTH
ADD1
ADD2
RDD1
RDD2
WRL1
RDL1
RDL2
WDS
WDH
ADS
ADH
RDH
WTL
Data Sheet U14040EJ4V0DS
°
C, V
Conditions
DD
= 4.0 to 5.5 V)
(1.5 + 2n)t
(2.5 + 2n)t
(1.5 + 2n)t
(0.5 + n)t
0.8t
0.8t
0.8t
2t
µ PD78F0034A, 78F0034AY
0.3t
0.8t
0.8t
CY
MIN.
CY
20
60
CY
40
10
CY
6
0
0
6
6
– 15
CY
CY
– 15
CY
CY
– 15
– 15
CY
CY
CY
+ 10
– 33
– 33
– 15
(2 + 2n)t
(3 + 2n)t
(2 + 2n)t
(3 + 2n)t
1.2t
1.2t
2.5t
2.5t
(2 + 2n)t
t
t
t
CY
CY
CY
1.2t
MAX.
100
CY
CY
CY
CY
60
– 43
– 43
– 25
CY
CY
CY
CY
CY
+ 30
+ 30
+ 25
+ 25
– 54
– 60
– 87
– 93
CY
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1/3)
33