AM29LV001BB-90EC Spansion Inc., AM29LV001BB-90EC Datasheet - Page 10

• Manufacturer Part Number: AM29LV001BB-90EC
• Manufacturer: Spansion Inc.

Specifications of AM29LV001BB-90EC

• Cell Type: NOR
• Density: 1Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 17b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 128K
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to
“Autoselect Command Sequence” on page 13
information.
I
active current specification for the write mode. The
Characteristics” on page 26
specification tables and timing diagrams for write
operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to
Status” on page 18
Characteristics” on page 26
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
V
VCC ± 0.3 V, the device will be in the standby mode, but
the standby current is greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
RESET#: Hardware Reset Pin.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
8
CC2
IH
.) If CE# and RESET# are held at V
in the DC Characteristics table represents the
for more information, and to
“Autoselect Mode” on page 9
for timing diagrams.
section contains timing
“Write Operation
IH
, but not within
for more
D A T A S H E E T
Am29LV001B
“AC
“AC
and
CC
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.The system may use the
RESET# pin to force the device into the standby mode.
Refer to
information.
Refer to the AC Characteristics tables for RESET#
parameters and to
diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
IL
but not within V
“Standby Mode” on page 8
Figure 14, on page 27
SS
±0.3 V, the standby current is
CC4
21557F4 May 5, 2006
SS
). If RESET# is held
±0.3 V, the device
CC5
for the timing
for more
in the DC
ACC
RP
+ 30
, the