JS28F128P30T85 Micron Technology Inc, JS28F128P30T85 Datasheet - Page 22

• Manufacturer Part Number: JS28F128P30T85
• Manufacturer: Micron Technology Inc

Specifications of JS28F128P30T85

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 85/17ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 23b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 8M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Compliant

5.0
Table 10: Bus Operations Summary
5.1
5.2
Note:
5.3
Datasheet
22
Read
Write
Output Disable
Standby
Reset
Notes:
1.
2.
3.
Bus Operation
Asynchronous
Synchronous
Refer to the
operation.
X = Don’t Care (H or L).
RST# must be at V
not be attempted.
Write operations with invalid V
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously
flows through if ADV# is held low. In synchronous mode, the address is latched by the
first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE#
and RST# must be V
Bus cycles to/from the P30 device conform to standard microprocessor bus operations.
Table 10
the device control signal inputs.
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus.
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first.
shows the bus cycle sequence for each of the supported device commands, while
Table 11, “Command Codes and Definitions” on page 24
Section 15.0, “AC Characteristics” on page 55
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
Table 12, “Command Bus Cycles” on page 26
RST#
SS
V
V
V
V
V
summarizes the bus operations and the logic levels that must be applied to
V
IH
IH
IH
IH
IH
IL
± 0.2 V to meet the maximum specified power-down current.
Running
CLK
X
X
X
X
X
IH
; CE# must be V
CC
ADV#
X
X
X
L
L
L
and/or V
CE#
H
X
L
L
L
L
PP
voltages can produce spurious results and should
IL
Table 12, “Command Bus Cycles” on page 26
).
OE#
H
H
X
X
L
L
for signal-timing details.
for valid DQ[15:0] during a write
WE#
H
H
H
X
X
L
describes each command. See
Deasserted
High-Z
High-Z
High-Z
High-Z
Driven
WAIT
DQ[15:0
Output
Output
High-Z
High-Z
High-Z
Input
]
August 2008
306666-12
Notes
2,3
1
2
2
P30