CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 82

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 10-30. Shift of SSF and SSV from SADR
10.6.9
The hardware diagram of the search subsystem of 31 devices is shown in Figure 10-57. Each of the four blocks in the diagram
represents a block of eight CYNSE70128 devices, except the last which has seven devices. The diagram for a block of eight
devices is shown in Figure 10-58. The following are the parameters programmed into the 31 devices.
Note
programmed with LRAM = 1 and LDEV = 1 (device number 30 in this case). All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (devices 0 through 29 in this case).
The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions defined in Table 10-31. For the purpose of
illustrating the timings, it is further assumed that there is only one device with the matching entry in each block. Figure 10-59
shows the timing diagram for a Search command in the 288-bit-configured table consisting of 31 devices for each of the eight
devices in block number 0. Figure 10-60 shows the timing diagram for a Search command in the 288-bit-configured table of 31
devices for all devices above the winning device in block number 1. Figure 10-61 shows the timing diagram for the globally winning
device (the final winner within its own and all blocks) in block number 1. Figure 10-62 shows the timing diagram for all the devices
below the globally winning device in block number 1. Figure 10-63, Figure 10-64, and Figure 10-65, respectively, show the timing
diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winning
device for block number 2. Figure 10-66, Figure 10-67, Figure 10-68, and Figure 10-69, respectively, show the timing diagrams
of the device above the globally winning device, the globally winning device, the devices below the globally winning device (except
device 30), and last device (device 30) for block number 3.
The 288-bit Search operation is pipelined and executes as follows. Four cycles from the last cycle of the Search command each
of the devices knows the outcome internal to it for that operation. In the fifth cycle from the Search command, the devices in a
block (which is less than or equal to eight devices resolving the winner within them using an LHI[6:0] and LHO[1:0] signalling
mechanism) arbitrate for a winner. In the sixth cycle after the Search command, the blocks of devices resolve the winning block
through a BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the winning block is the global winning device
for the Search operation.
Table 10-31. Hit/Miss Assumption
Document #: 38-02040 Rev. *F
• First thirty devices (devices 0–29): CFG = 1010101010101010, TLSZ = 10, HLAT = 000, LRAM = 0, and LDEV = 0.
• Thirty-first device (device 30): CFG = 1010101010101010, TLSZ = 10, HLAT = 000, LRAM = 1, and LDEV = 1.
. All 31 devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be
Search Number
288-bit Search on Tables Configured as x288 Using up to 31 CYNSE70128 Devices
Block 0
Block 1
Block 2
Block 3
HLAT
101
110
111
Miss
Miss
Miss
Hit
1
Number of CLK Cycles
Miss
Miss
Hit
Hit
2
5
6
7
CYNSE70128
Miss
Miss
Hit
Hit
3
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