CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet
CYNSE70128-83BGC
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CYNSE70128-83BGC Summary of contents
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... CYNSE70128 Network Search Engine Cypress Semiconductor Corporation Document #: 38-02040 Rev. *F • 3901 North First Street • CYNSE70128 , San Jose CA 95134 • 408-943-2600 Revised January 28, 2005 ...
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... Search on Tables Configured as x144 Using CYNSE70128 Devices ................ 59 10.6.7 288-bit Search on Tables Configured as x288 Using a Single CYNSE70128 Device .................. 74 10.6.8 288-bit Search on Tables Configured as x288 Using up to Eight CYNSE70128 Devices ............ 76 10.6.9 288-bit Search on Tables Configured as x288 Using CYNSE70128 Devices ................ 82 10.6.10 Mixed-Size Searches on Tables Configured with Different Widths Using a CYNSE70128 with CFG_L LOW ...
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... Power Consumption .............................................................................................................. 123 14.0 APPLICATION ........................................................................................................................... 124 15.0 JTAG (1149.1) TESTING ........................................................................................................... 124 16.0 ELECTRICAL SPECIFICATIONS .............................................................................................. 125 17.0 AC TIMING WAVEFORMS ........................................................................................................ 126 17.1 Special Note for MULTI_HIT Function on the CYNSE70128 ................................................ 129 18.0 PINOUT DESCRIPTION ............................................................................................................. 130 19.0 ORDERING INFORMATION ...................................................................................................... 135 20.0 PACKAGE DIAGRAM ................................................................................................................ 136 Document #: 38-02040 Rev. *F ...
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... Figure 7-2. Addressing the Global Mask Register Array ....................................................................... 16 Figure 8-1. CYNSE70128 Database Width Configuration ..................................................................... 19 Figure 8-2. Multiwidth Database Configurations Example ..................................................................... 21 Figure 9-1. Addressing the CYNSE70128 Data and Mask Arrays ........................................................ 21 Figure 10-1. Single-Location Read Cycle Timing .................................................................................. 23 Figure 10-2. Burst Read of the Data and Mask Arrays (BLEN = 4) ....................................................... 24 Figure 10-3 ...
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... Figure 12-4. SRAM Read Timing for Device Number Block of Eight Devices ........................... 110 Figure 12-5. Table of 31 Devices Made of Four Blocks....................................................................... 111 Figure 12-6. SRAM Read Through Device Number Block of 31 Devices (Device Number 0 Timing)................................................................................................................... 112 Document #: 38-02040 Rev. *F LIST OF FIGURES (continued) CYNSE70128 Page 5 of 137 ...
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... Figure 12-12. Table of 31 Devices (Four Blocks) ................................................................................ 118 Figure 12-13. SRAM Write Through Device Number Bank of 31 Devices (Device 0 Timing) ... 119 Figure 12-14. SRAM Write Through Device Number Bank of 31 CYNSE70128 Devices (Device Number 30 Timing)................................................................................................................. 120 Figure 13-1. Power-up Sequence (CLK2x).......................................................................................... 121 Figure 13-2 ...
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... Table 10-35. Latency of SRAM Write Cycle from Second Cycle of Learn Instruction ........................ 101 Table 12-1. SRAM Address ................................................................................................................ 106 Table 12-2. Required Idle Cycles between Commands ...................................................................... 121 Table 15-1. Supported Operations ..................................................................................................... 124 Table 15-2. TAP Device ID Register ................................................................................................... 125 Table 16-1. DC Electrical Characteristics for CYNSE70128 .............................................................. 125 Document #: 38-02040 Rev. *F LIST OF TABLES CYNSE70128 Page 7 of 137 ...
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... Table 16-2. Operating Conditions for CYNSE70128 .......................................................................... 126 Table 17-1. AC Timing Parameters with CLK2X ................................................................................ 126 Table 17-2. AC Timing Parameters with CLK1X ................................................................................ 127 Table 17-3. 2.5V AC Table for Test Condition of CYNSE70128 ........................................................ 127 Table 18-1. Pinout Descriptions for Pinout Diagram ........................................................................... 132 Table 19-1. Ordering Information ........................................................................................................ 135 Document #: 38-02040 Rev ...
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... Associative Processing Technology™ (APT) and is designed high-performance, pipelined, synchronous, 64K-entry NSE. The CYNSE70128 database entry size can be 72 bits, 144 bits, or 288 bits. In the 72-bit entry mode, the size of the database is 64K entries. In the 144-bit mode, the size of the database is 32K entries, and in the 288-bit mode, the size of the database is 16K entries ...
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... Data Array Configurable as 64K × 72 32K × 144 16K × 288 Mask Array LHI[6:0] Arbitration BHI[2:0] Logic FULL FULO[1:0] CYNSE70128 TAP TAP Controller SADR[23:0] OE_L Pipeline and WE_L SRAM Control CE_L ALE_L LHO[1:0] BHO[2:0] ...
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... CYNSE70128 samples control and data signals on both the edges of CLK1X (if CLK1X is supplied). CYNSE70128 samples all the data and control pins on the positive edge of CLK2X if the CLK2X and PHS_L signals are supplied. All signals are driven out of the device on the rising edge of CLK1X if CLK1X is supplied, and are driven on the rising edge of CLK2X (when PHS_L is low) if CLK2X is supplied ...
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... See Table 12-1 for the details of the generated SRAM address database of multiple CYNSE70128s, each corresponding bit of SADR from all cascaded devices must be connected. CE_L T SRAM Chip Enable: CYNSE70128s, CE_L of all cascaded devices must be connected. This signal is then driven by only one of the devices. WE_L T SRAM Write Enable: CYNSE70128s, WE_L of all cascaded devices must be connected together ...
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... Clocks If the CLK_MODE pin is LOW, CYNSE70128 receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X and generate a CLK, as shown in Figure 5-1. The CYNSE70128 uses CLK2X and CLK for internal operations. Also noted on “Cycle A End” CLK2X PHS_L ...
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... CLK2X PHS_L Use for CLK2X mode CLK1X Use for CLK1X mode Figure 5-3. CYNSE70128 Clocks for All Timing Diagrams Document #: 38-02040 Rev. *F CYNSE70128 Page 14 of 137 ...
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... Registers All registers in the CYNSE70128 are 72 bits wide. The CYNSE70128 contains 16 pairs of comparand storage registers, 16 pairs of global mask registers (GMRs), eight search successful index registers and one each of command, information, burst Read, burst Write, and next-free address registers. Table 7-1 provides an overview of all the CYNSE70128 registers. The registers are ordered in ascending address order ...
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... Search operation. 0 Reserved. 0 Valid. During Search operation in a depth-cascaded configuration, the device that is a global winner in a match sets this bit to 1. This bit updates only when the device is a global winner in a Search operation. 0 Reserved. CYNSE70128 . In 72-bit Search and Write Note ...
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... Last Device on the SRAM Bus. When set, this device is the last device on the SRAM bus in the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and ALE_L signals. In cycles where no CYNSE70128 device in a depth cascaded table drives these signals, this devices drives the signals as follows: SADR = 24’ ...
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... Initial Value 0001 Revision Number. This is the current device revision number. Numbers start at one and increment by one for each revision of the device. 001 This is the CYNSE70128 implementation number. 0 Reserved. 00000100 This is the device identification number. 1101_1100_0111_1111 Manufacturer ID. This field is the same as the manufac- turer identification number and continuation bits in the TAP controller ...
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... NSE Architecture and Operation Overview The CYNSE70128 consists of 64K × 72-bit storage cells referred to as data bits. There is a mask cell corresponding to each data cell. Figure 8-1 shows the three organizations of the device based on the value of the CFG bits in the command register. ...
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... The global winning device drives the SRAM bus, SSV, and the SSF signals. In case of a Search failure, the device(s) with the LDEV and LRAM bits set drive(s) the SRAM bus, SSF, and SSV signals. The CYNSE70128 device can be configured to contain tables of different widths, even within the same chip. Figure 8-2 shows a sample configuration of different widths. ...
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... Figure 9-1. Addressing the CYNSE70128 Data and Mask Arrays 10.0 Commands A master device such as an ASIC controller issues commands to the CYNSE70128 device using the command valid (CMDV) signal and the CMD bus. The following subsections describe the operation of the commands. 10.1 Command Codes The CYNSE70128 implements four basic commands, shown in Table 10-1 ...
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... NFA register) using the Learn instruction. 10.2 Commands and Command Parameters Table 10-2 lists the CMD bus fields that contain the CYNSE70128 command parameters and their respective cycles. Each command is described separately in the subsections that follow. Table 10-2. Command Parameters [9, 10] ...
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... Table 10-4 and Table 10-5. The host ASIC selects the CYNSE70128 for which ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70128 with the LDEV bit set. The host ASIC also supplies SADR[23:21] on CMD[8:6] in cycle A of the Read instruction if the Read is directed to the external SRAM. ...
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... Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[ using CMDV = 1 and the address supplied on the DQ bus, as shown in Table 10-6. The host ASIC selects the CYNSE70128 where ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70128 with the LDEV bit set. ...
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... A Address Data Figure 10-3. Single Write Cycle Timing . The latency of the SRAM Write will be different than the one Note CYNSE70128 DQ[15:0] . These 16 bits come from the internal Do not care register (RBURADR) which increments for each access. . These 16 bits come from the internal ...
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... Cycle 2: The host ASIC drives the DQ[71:0] with the data to be written to the data or mask array location of the selected device. The CYNSE70128 writes the data from the DQ[71:0] bus only to the subfield that has the corresponding mask bit set the GMR specified by the index {CMD[10],CMD[5:3]} supplied in cycle 1. ...
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... GMR specified by the index {CMD[10],CMD[5:3]} supplied in cycle 1. The CYNSE70128 drives the EOT signal low from cycle 3 to cycle n; the CYNSE70128 drives the EOT signal high in cycle specified in the BLEN field of the WBURREG). • Cycle TheCYNSE70128 drives the EOT signal LOW. ...
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... DQ bus during cycles A Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 Search1 Hit Search2 6 5 CYNSE70128 LHO[1] CYNSE70128 cycle cycle cycle cycle Search4 Search3 Miss Hit Miss LHI SRAM LHO[0] Page 28 of 137 ...
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... Document #: 38-02040 Rev GMR 71 Location address 65535 CFG = 0000000000000000 (288-bit configuration) Figure 10-7. x72 Table with One Device Max Table Size 64K × 72 bits 512K × 72 bits 1984K × 72 bits Number of CLK Cycles CYNSE70128 (First matching entry) Latency in CLK Cycles Page 29 of 137 ...
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... Search on Tables Configured as ×72 Using up to Eight CYNSE70128 Devices The hardware diagram of the search subsystem of eight devices is shown in Figure 10-8. The following are the parameters programmed into the eight devices. • First seven devices (device 0–6): CFG = 0000000000000000, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0. ...
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... BHI[2:0] BHI[2:0] BHI[2:0] Figure 10-8. Hardware Diagram for a Table with Eight Devices Document #: 38-02040 Rev CYNSE70128 #0 LHO[ CYNSE70128 #1 LHO[ CYNSE70128 #2 LHO[ CYNSE70128 # CYNSE70128 #4 LHO[ LHI LHI CYNSE70128 #5 LHO[ LHI LHI CYNSE70128 #6 LHO[ LHI LHI CYNSE70128 #7 CYNSE70128 SRAM LHI LHO[ LHI LHO[0] 3 ...
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... Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-9. Timing Diagram for 72-bit Search Device Number 0 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle cycle cycle ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-10. Timing Diagram for 72-bit Search Device Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Local on this winner device.) but not global winner.) ...
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... SSR[0:7]). The DQ[71:0] continues to carry the 72-bit data to be compared. Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Local but not on this global winner) device ...
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... 524287 CFG = 0000000000000000 devices (72-bit configuration) Figure 10-12. x72 Table with Eight Devices Max Table Size 64K × 72 bits 512K × 72 bits 1984K × 72 bits Number of CLK Cycles CYNSE70128 0 GMR K 0 (First matching entry) Latency in CLK Cycles Page 35 of 137 ...
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... The hardware diagram of the search subsystem of 31 devices is shown in Figure 10-13. Each of the four blocks in the diagram represents eight CYNSE70128 devices (except the last, which has seven devices). The diagram for a block of eight devices is shown in Figure 10-14. The following are the parameters programmed into the 31 devices. ...
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... Block 1 (Devices 8–15) CYNSE70128s BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 Block 2 (Devices 16–23) CYNSE70128s BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 Block 3 (Devices 24–30) CYNSE70128s BHO[2] BHO[1] CYNSE70128 BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] BHI[0] BHO[0] Page 37 of 137 ...
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... BHI[2:0] BHI[2:0] 3 BHI[2:0] BHI[2:0] 3 Figure 10-14. Hardware Diagram for a Block Eight Devices Document #: 38-02040 Rev CYNSE70128 #0 LHO[ CYNSE70128 #1 LHO[ CYNSE70128 #2 LHO[ CYNSE70128 # CYNSE70128 #4 LHO[ LHI LHI CYNSE70128 #5 LHO[ LHI LHI CYNSE70128 #6 LHO[ LHI LHI CYNSE70128 #7 CYNSE70128 LHI LHO[ LHI LHO[ LHI ...
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... Figure 10-15. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 39 of 137 ...
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... Figure 10-16. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 40 of 137 ...
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... Figure 10-17. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (This on device this global device.) winner.) Search2 Search4 (Miss (Miss ...
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... Figure 10-18. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 42 of 137 ...
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... Figure 10-19. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 43 of 137 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-20. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Hit on but this not device.) winner ...
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... Figure 10-21. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on on this this device.) device.) Page 45 of 137 ...
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... Figure 10-22. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 46 of 137 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-23. Timing Diagram for Globally Winning Device in Block Number 3 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Global (Miss winner this device.) Search2 Search4 ...
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... Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 the Last Device [Device 30]) CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on on this this device.) device.) Page 48 of 137 ...
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... GMRs selected for the compare must be programmed with the same value. Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle cycle cycle Search1 Search3 (Hit on (Hit on some some device device above.) above.) Search2 Search4 (Global (Hit on miss ...
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... GMR K 71 Location address 2031615 CFG = 0000000000000000 (72-bit configuration) Figure 10-26. x72 Table with 31 Devices Max Table Size 64K × 72 bits 512K × 72 bits 1984K × 72 bits Number of CLK Cycles CYNSE70128 0 0 (First matching entry) Latency in CLK Cycles Page 50 of 137 ...
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... Search on Tables Configured as x144 Using a Single CYNSE70128 Device Figure 10-27 shows the timing diagram for a Search command in the 144-bit-configured table (CFG = 0101010101010101) consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, and LDEV = 1. The hardware diagram for this search subsystem is shown in Figure 10-28 ...
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... Figure 10-29. x144 Table with One Device Max Table Size 32K × 144 bits 256K × 144 bits 992K × 144 bits Number of CLK Cycles CYNSE70128 . The matching address is always going to Note 0 0 (First matching entry) Latency in CLK Cycles ...
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... Search on Tables Configured as x144 Using up to Eight CYNSE70128 Devices The hardware diagram of the search subsystem of eight devices is shown in Figure 10-30. The following are parameters programmed into the eight devices. • First seven devices (devices 0–6): CFG = 0101010101010101, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0. ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Figure 10-30. Hardware Diagram for a Table with Eight Devices Document #: 38-02040 Rev CYNSE70128 #0 LHO[ CYNSE70128 #1 LHO[ CYNSE70128 #2 LHO[1] BHI[2: CYNSE70128 #3 LHO[ CYNSE70128 # LHI LHI CYNSE70128 #5 LHO[ LHI CYNSE70128 #6 LHO[ LHI LHI CYNSE70128 #7 CYNSE70128 LHI LHO[ LHI LHO[0] ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-31. Timing Diagram for 144-bit Search Device Number 0 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (This (This device device ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-32. Timing Diagram for 144-bit Search Device Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Local on this winner device.) but not global winner.) Search4 ...
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... GMR Index in the command’s cycle A. Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Local but not (Miss on global winner) this device) Search4 Search2 ...
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... Location address 262142 CFG = 0101010101010101 (144-bit configuration) Figure 10-34. x144 Table with Eight Devices Max Table Size 32K × 144 bits 256K × 144 bits 992K × 144 bits Number of CLK Cycles CYNSE70128 0 Odd B 0 (First matching entry) Latency in CLK Cycles ...
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... The hardware diagram of the search subsystem of 31 devices is shown in Figure 10-35. Each of the four blocks in the diagram represents a block of eight CYNSE70128 devices (except the last, which has seven devices). The diagram for a block of eight devices is shown in Figure 10-36. Following are the parameters programmed into the 31 devices. ...
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... Block 1 (devices 8–15) CYNSE70128s BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 Block 2 (devices 16–23) CYNSE70128s BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 Block 3 (devices 24–30) CYNSE70128s BHO[2] BHO[1] CYNSE70128 BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] BHI[0] BHO[0] Page 60 of 137 ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] 3 Figure 10-36. Hardware Diagram for a Block Eight Devices Document #: 38-02040 Rev CYNSE70128 #0 LHO[ CYNSE70128 #1 LHO[ CYNSE70128 #2 LHO[ CYNSE70128 # CYNSE70128 #4 LHO[ LHI LHI CYNSE70128 #5 LHO[ LHI LHI CYNSE70128 #6 LHO[ LHI LHI CYNSE70128 #7 CYNSE70128 LHI LHO[ LHI LHO[ LHI ...
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... Figure 10-37. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 62 of 137 ...
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... Figure 10-38. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search1 Search3 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 63 of 137 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-39. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (This on device this global device.) winner.) ...
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... Figure 10-40. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 65 of 137 ...
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... Figure 10-41. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 66 of 137 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-42. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Hit on But this not device.) winner.) ...
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... Figure 10-43. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on on this this device.) device.) Page 68 of 137 ...
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... Figure 10-44. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Page 69 of 137 ...
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... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-45. Timing Diagram for Globally Winning Device in Block Number 3 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 CYNSE70128 cycle cycle cycle Search1 Search3 (Global (Miss winner.) on this device.) Search2 Search4 (Miss ...
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... Search3 Search1 Search2 Search4 Except Device 30 (the Last Device) CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 Search4 (Miss (Miss on on this this device.) device.) Page 71 of 137 ...
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... The CMD[2] signal must be driven to logic 0. Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search3 Search1 Search2 Search4 Depth-Cascaded Table) CYNSE70128 cycle cycle cycle Search1 Search3 (Hit (Hit on on some some device device above.) above ...
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... CFG = 0101010101010101 (144-bit configuration) Figure 10-48. x144 Table with 31 Devices Max Table Size 32K × 144 bits 256K × 144 bits 992K × 144 bits Number of CLK Cycles CYNSE70128 . The Learn Note . During 144-bit searches of 144- Note 0 Odd B 0 (First matching entry) ...
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... Search on Tables Configured as x288 Using a Single CYNSE70128 Device Figure 10-49 shows the timing diagram for a Search command in the 288-bit-configured table (CFG = 1010101010101010) consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, and LDEV = 1. The hardware diagram for this search subsystem is shown in Figure 10-50 ...
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... CMD[ signals that the Search is a x288-bit search. CMD[8:3] in this cycle is ignored. . The matching address is always going to be location four- Note CFG = 1010101010101010 (288-bit configuration) Figure 10-51. x288 Table with One Device CYNSE70128 LHI SRAM LHO[ (First matching entry) (First matching entry) Page 75 of 137 ...
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... Search on Tables Configured as x288 Using up to Eight CYNSE70128 Devices The hardware diagram of the search subsystem of eight devices is shown in Figure 10-52. The following are the parameters programmed in the eight devices. • First seven devices (devices 0–6): CFG = 1010101010101010, TLSZ = 01, HLAT = 000, LRAM = 0, and LDEV = 0. ...
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... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Figure 10-52. Hardware Diagram for a Table with Eight Devices Document #: 38-02040 Rev CYNSE70128 #0 LHO[ CYNSE70128 #1 LHO[ CYNSE70128 #2 LHO[1] BHI[2: CYNSE70128 #3 LHO[ CYNSE70128 # LHI LHI CYNSE70128 #5 LHO[ LHI CYNSE70128 #6 LHO[ LHI LHI CYNSE70128 #7 CYNSE70128 LHI LHO[ LHI LHO[0] ...
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... Figure 10-53. Timing Diagram for 288-bit Search Device Number 0 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 Search1 (This device is the global winner.) CYNSE70128 cycle cycle cycle Search2 Search3 (Miss (Miss on this on this device.) device.) Page 78 of 137 ...
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... Figure 10-54. Timing Diagram for 288-bit Search Device Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 Search1 (Miss on this device.) CYNSE70128 cycle cycle cycle Search3 (Miss on this device.) Search2 (This device is global winner.) Page 79 of 137 ...
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... Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 Search1 (Miss on this device.) . CMD[ signals that the search is a 288-bit search. CMD[8:3] Note CYNSE70128 cycle cycle cycle Search2 Search3 (Global (Miss miss.) on this device.) Page 80 of 137 ...
Page 81
... Figure 10-56. x288 Table with Eight Devices Max Table Size 16K × 288 bits 128K × 288 bits 496K × 288 bits Number of CLK Cycles CYNSE70128 . The matching address is always Note 0 Must be same in each of the eight devices 0 (First matching entry) ...
Page 82
... The hardware diagram of the search subsystem of 31 devices is shown in Figure 10-57. Each of the four blocks in the diagram represents a block of eight CYNSE70128 devices, except the last which has seven devices. The diagram for a block of eight devices is shown in Figure 10-58. The following are the parameters programmed into the 31 devices. ...
Page 83
... CYNSE70128s BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 block 2 (devices 16–23) CYNSE70128s BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 block 3 (devices 24–30) CYNSE70128s BHO[2] BHO[1] CYNSE70128 BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] BHI[0] BHO[0] Page 83 of 137 ...
Page 84
... BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] 3 Figure 10-58. Hardware Diagram for a Block Eight Devices Document #: 38-02040 Rev CYNSE70128 #0 LHO[ CYNSE70128 #1 LHO[ CYNSE70128 #2 LHO[ CYNSE70128 # CYNSE70128 #4 LHO[ LHI LHI CYNSE70128 #5 LHO[ LHI LHI CYNSE70128 #6 LHO[ LHI LHI CYNSE70128 #7 CYNSE70128 LHI LHO[ LHI LHO[ LHI ...
Page 85
... Figure 10-59. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70128 cycle cycle cycle Search1 Search3 (Misson (Misson this device) this device.) Search2 (Miss on this device.) Page 85 of 137 ...
Page 86
... Figure 10-60. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 (Miss on this device.) Page 86 of 137 ...
Page 87
... Figure 10-61. Timing Diagram for Globally Winning Device in Block Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70128 cycle cycle cycle cycle cycle Search1 Search3 (This (Miss on device this device.) global Search2 winner.) (Miss on this device.) Page 87 of 137 ...
Page 88
... Figure 10-62. Timing Diagram for Devices Below the Winning Device in Block Number 1 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device.) Search2 (Miss on this device.) Page 88 of 137 ...
Page 89
... Figure 10-63. Timing Diagram for Devices Above the Winning Device in Block Number 2 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss on (Miss on this device.) this device; hit in block 0 or block 1.) Search2 (Miss on this device.) Page 89 of 137 ...
Page 90
... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-64. Timing Diagram for Globally Winning Device in Block Number 2 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70128 cycle cycle cycle Search3 Search1 (Hit (Miss but on not this winner ...
Page 91
... Figure 10-65. Timing Diagram for Devices Below the Winning Device in Block Number 2 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 (Miss on this device.) Page 91 of 137 ...
Page 92
... Figure 10-66. Timing Diagram for Devices Above the Winning Device in Block Number 3 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70128 cycle cycle cycle Search1 Search3 (Miss (Miss on on this this device.) device.) Search2 (Miss on this device.) Page 92 of 137 ...
Page 93
... Note: Each bit in LHO[1:0] is the same logical signal. Figure 10-67. Timing Diagram for Globally Winning Device in Block Number 3 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle Search2 Search3 Search1 CYNSE70128 cycle cycle cycle cycle cycle Search3 Search1 (Miss (Global on winner.) this Search2 device.) (Hit ...
Page 94
... Figure 10-68. Timing Diagram for Devices Below the Winning Device in Block Number 3 Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle Search2 Search1 Search3 Except Device 30 (the Last Device) CYNSE70128 cycle cycle cycle cycle cycle Search Search3 (Miss on (Miss on this device.) this device.) Search2 (Miss on this device.) Page 94 of 137 ...
Page 95
... Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle Search2 Search1 Search3 CMD[ signals that the search is a x288-bit search. CMD[8:6] is ignored in this cycle. CYNSE70128 cycle cycle cycle cycle ...
Page 96
... Figure 10-70. x288 Table with 31 Devices Max Table Size 16K × 288 bits 128K × 288 bits 496K × 288 bits Number of CLK Cycles CYNSE70128 . The matching address is always Note Must be same in each of the 31 devices Latency in CLK Cycles 4 ...
Page 97
... DQ[71:70 each of the and D cycles of the ×288-bit search (Search3). By having table designation bits, the CYNSE70128 enables the creation of many tables in a bank of NSEs of different widths. Figure 10-72 shows the sample table. Two bits in each 72-bit entry will need to designated as the table number bits. One example choice can be the 00 values for the table configured as × ...
Page 98
... Failure will cause contention on SADR, CE_L, WE_L and can potentially cause damage to the device(s). Similarly, when NSEs using multiple CYNSE70128s are cascaded, SSF and SSV (also three-state signals) are tied together. In order to eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. For nonsearch cycles or Search cycles with a global miss the SSF and SSV signals are driven by the device with the LDEV bit set ...
Page 99
... The global FULL signal indicates to the table controller (the host ASIC) that all entries within a block are occupied and that no more entries can be learned. The CYNSE70128 updates the signal after each Write or Learn command to a data array. The Learn command generates a Write cycle to the external SRAM, also using the NFA register as part of the SRAM address (see ”SRAM Addressing” ...
Page 100
... DQ z SADR[23:0] z CE_L z WE_L z OE_L z SSV z SSF TLSZ = 01, LRAM = 0, LDEV = 0. Figure 10-74. Timing Diagram of Learn (Except on the Last Device [TLSZ = 01]) Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Learn2 X Learn1 X Comp2 Comp1 CYNSE70128 cycle cycle cycle Page 100 of 137 ...
Page 101
... CMD[6] must be set the Learn is being performed on a 72-bit-configured table, and the Learn is being performed on a 144-bit-configured table. Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Learn2 X Learn1 X Comp2 Comp1 Latency in CLK Cycles CYNSE70128 cycle cycle cycle Page 101 of 137 ...
Page 102
... The LHI[6:0] signals for a device are connected to LHO signals of the upstream devices. The host ASIC must program the TLSZ to 01 for each eight devices in a block. Only a single device drives the SRAM bus in any single cycle. Document #: 38-02040 Rev. *F CYNSE70128 Page 102 of 137 ...
Page 103
... Depth-Cascading Devices (Four Blocks) Figure 11-2 shows how to cascade up to four blocks. Each block contains up to eight CYNSE70128 devices except the last, and the interconnection within each was shown in the previous subsection with the cascading eight devices in a block. The interconnection between blocks for depth-cascading is important. For each Search, a block asserts BHO[2], BHO[1], and BHO[0] ...
Page 104
... BHI[2] BHI[1] Block of 8 Block 2 (devices 16–23) CYNSE70128s BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 Block 3 (devices 24-30) CYNSE70128s BHO[2] BHO[1] Figure 11-2. Depth-Cascading Four Blocks CYNSE70128 BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] BHI[0] BHO[0] Page 104 of 137 ...
Page 105
... NFA and SSR registers. ADR[15:0] contains the address supplied on the DQ bus during PIO access to the CYNSE70128. Command bits 8, 7, and 6 {CMD[8:6]} are passed from the command to the SRAM address bus. See ”Commands” on page 21, for more information. ID[4:0] is the ID of the device driving the SRAM bus (see ” ...
Page 106
... At the end of cycle 6, the selected device floats ACK in a three-state condition, and a new command can begin. Document #: 38-02040 Rev [20:16 ID[4: ID[4: ID[4: ID[4: ID[4:0] . SRAM Write is a pipelined operation—new Note CYNSE70128 [15:0] Index[15:0] NFA[15:0] ADR15:0] ADR[15:0] SSR[15:0] Page 106 of 137 ...
Page 107
... The following explains the SRAM Read operation completed through a table eight devices using the following parameters: TLSZ = 01. Figure 12-2 diagrams a block of eight devices. The following assumes that SRAM access is successfully achieved through CYNSE70128 device number 0. Figure 12-3 and Figure 12-4 show timing diagrams for device number 0 and device number 7, respectively. ...
Page 108
... CMD[10:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Document #: 38-02040 Rev CYNSE70128 #0 LHO[ CYNSE70128 #1 LHO[ CYNSE70128 #2 LHO[1] BHI[2: CYNSE70128 #3 LHO[ CYNSE70128 # LHI LHI CYNSE70128 #5 LHO[ LHI CYNSE70128 #6 LHO[ LHI LHI CYNSE70128 #7 Figure 12-2. Table of a Block of Eight Devices CYNSE70128 LHI LHO[ LHI LHO[0] ...
Page 109
... ALE_L z z SADR z SSV z z SSF TLSZ = 01, HLAT = 000, LRAM = 0, LDEV = 0. Figure 12-3. SRAM Read Through Device Number Block of Eight Devices Document #: 38-02040 Rev. *F cycle cycle cycle cycle Read Address CYNSE70128 cycle cycle cycle Address Driven by Selected CYNSE70128 Page 109 of 137 ...
Page 110
... TLSZ = 10. The diagram of such a table is shown in Figure 12-5. The following assumes that SRAM access is being accomplished through CYNSE70128 device number 0, that device number 0 is the selected device. Figure 12-6 and Figure 12- 7 show the timing diagrams for device number 0 and device number 30, respectively. ...
Page 111
... Block 1 (devices 8–15) CYNSE70128s BHO[2] BHO[1] BHI[2] BHI[1] Block of 8 Block 2 (devices 16–23) CYNSE70128s BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 Block 3 (devices 24–30) CYNSE70128s BHO[2] BHO[1] CYNSE70128 BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] GND BHI[0] BHO[0] BHI[0] BHO[0] Page 111 of 137 ...
Page 112
... TLSZ = 10, HLAT = 010, LRAM = 0, LDEV = 0. Figure 12-6. SRAM Read Through Device Number Block of 31 Devices (Device Number 0 Timing) Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Read Address Address CYNSE70128 cycle cycle cycle driven by the selected CYNSE70128 Page 112 of 137 ...
Page 113
... Writes into the SRAM are not supported. • Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. • Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. ...
Page 114
... Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. • Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. At the end of cycle 3, a new command can begin. The Write is a pipelined operation. The Write cycle appears at the SRAM bus, however, with the same latency as that of a Search instruction, as measured from the second cycle of the Write command ...
Page 115
... CMD[10:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] BHI[2:0] Document #: 38-02040 Rev CYNSE70128 #0 LHO[ CYNSE70128 #1 LHO[ CYNSE70128 #2 LHO[1] BHI[2: CYNSE70128 #3 LHO[ CYNSE70128 # LHI LHI CYNSE70128 #5 LHO[ LHI CYNSE70128 #6 LHO[ LHI LHI CYNSE70128 #7 Figure 12-9. Table of a Block of Eight Devices CYNSE70128 LHI LHO[ LHI LHO[0] ...
Page 116
... ALE_L z SADR[23:0] z ACK z SSV z SSF TLSZ = 01, HLAT = XXX, LRAM = 0, LDEV = 0. Figure 12-10. SRAM Write Through Device Number Block of Eight Devices Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Write Address x x Address CYNSE70128 cycle cycle cycle Page 116 of 137 ...
Page 117
... Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. • Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. At the end of cycle 3, a new command can begin. The Write is a pipelined operation. The Write cycle appears at the SRAM bus, however, with the same latency as that of a Search instruction, as measured from the second cycle of the Write command ...
Page 118
... Block of 8 Block 2 (devices 16–23) CYNSE70128s BHO[2] BHO[1] BHI[2] BHI[1] Block of 7 Block 3 (devices 24–30) CYNSE70128s BHO[2] BHO[1] Figure 12-12. Table of 31 Devices (Four Blocks) CYNSE70128 BHI[0] GND SRAM BHO[0] BHI[0] GND BHO[0] BHI[0] GND BHO[0] BHI[0] BHO[0] Page 118 of 137 ...
Page 119
... ACK z SSV z SSF TLSZ = 10, HLAT = XXX, LRAM = 0, LDEV = 0. Figure 12-13. SRAM Write Through Device Number Bank of 31 Devices (Device 0 Timing) Document #: 38-02040 Rev. *F cycle cycle cycle cycle cycle cycle cycle Write Address x x CYNSE70128 cycle cycle cycle Address z Page 119 of 137 ...
Page 120
... SSV 0 SSF TLSZ = 10, HLAT = XXX, LRAM = 1, LDEV = 1. Figure 12-14. SRAM Write Through Device Number Bank of 31 CYNSE70128 Devices 12.9 Timing Sequences for Back-to-Back Operations Table 12-2 shows the idle cycle requirements between operations. The operations in the second column represent operations already performed, and the operations in the first row are those we would like to perform next. ...
Page 121
... The SRAM operation needs to insert idle cycles to avoid SADR bus contention with previous SEARCH. Document #: 38-02040 Rev. *F SEARCH READ WRITE No Wait / (2 No Wait No Wait 13 + TLSZ 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 2 2 CYNSE70128 LEARN SRAM TLSZ /(TLSZ No Wait + HLAT Page 121 of 137 ...
Page 122
... Power CYNSE70128 has two separate power supplies, one for the core (V 13.1 Power-up Sequence Proper power-up sequence is required to correctly initialize the Cypress NSEs before functional access to the device can begin. RST_L and TRST_L should be held low before the power supplies ramp-up. RST_L must be set low for a duration of time afterward and then set high ...
Page 123
... Hit and All Search Miss) assume the I/Os switch 50% of the time Absolute Worst Case (75C) All Searches Miss (75C) 8 All Searches Hit (75C Document #: 38-02040 Rev. *F Power Consumption of CYNSE70128 Frequency (MHz) Figure 13-3. Power Consumption of CYNSE70128 CYNSE70128 Page 123 of 137 100 ...
Page 124
... Application Figure 14-1 shows how an NSE subsystem can be formed using a host ASIC and an CYNSE70128 bank. It also shows how this NSE subsystem is integrated in a switch or router. The CYNSE70128 can access synchronous and asynchronous SRAMs by allowing the host ASIC to set the same HLAT parameter in all NSEs within a bank of NSEs. ...
Page 125
... LSB [0] 1 16.0 Electrical Specifications This section describes the electrical specifications, capacitance, operating conditions, DC characteristics, and AC timing param- eters for the CYNSE70128, as shown in Table 16-1 and Table 16-2. Table 16-1. DC Electrical Characteristics for CYNSE70128 Parameter Description I Input leakage current LI I ...
Page 126
... Ambient operating temperature A (Industrial) Supply voltage tolerance 17.0 AC Timing Waveforms Table 17-1 and Table 17-2 show the AC timing parameters for the CYNSE70128 device; Table 17-3 shows the same parameters but for 2.5V. Table 17-1. AC Timing Parameters with CLK2X Row Parameter 1 f CLK2X frequency. ...
Page 127
... Rising edge of CLK1X to SRAM bus high-Z. CKHSHZ 14 t Rising edge of CLK1X to SRAM bus low-Z. CKHSLZ Table 17-3. 2.5V AC Table for Test Condition of CYNSE70128 Input pulse levels (V = 3.3V) DDQ Input pulse levels (V = 2.5V) DDQ Input rise and fall times measured at 0.3V and 2.7V (V Input rise and fall times measured at 0 ...
Page 128
... AC Load Ω 192 Ω 175 Figure 17-3. I/O Output Load Equivalent for CYNSE70128 Figure 17-4 shows timing waveform diagrams for CLK2X. 25. Output loading is specified with pF Figure 17-3. Transition is measured at ± 200 mV from steady-state voltage. L 26. The load used for VOH, VOL testing is shown in Figure 17-3. ...
Page 129
... Special Note for MULTI_HIT Function on the CYNSE70128 General Description: The CYNSE70128 device provides a “MULTI_HIT” signal as an output. The purpose of this signal is to indicate the occurrence of a multiple hit on a Search in the search engine. Correct Usage: In order to ensure correct function for MULTI_HIT on CYNSE70128: • ...
Page 130
... Pinout Description In the following figure and table, the CYNSE70128 device pinout diagram and descriptions are shown (see Figure 18-1 and Table 18-1 RST_L FULL FULO1 FULI6 EOT ACK FULO0 DDQ DDQ DQ68 DQ70 DQ66 4 DDQ DQ62 DQ64 DQ60 DDQ DD SS ...
Page 131
... Ground AE11 Ground AE12 Ground AE13 Ground AE14 Ground AE15 Input AE16 I/O AE17 1.5V/1.65V AE18 1.5V/1.65V AE19 1.5V/1.65V AE2 1.5V/1.65V AE20 CYNSE70128 Signal Name Signal Type CMD[2] Input V 1.5V/1.65V DD V Ground SS FULL Output-T ACK Output-T VSS Ground V 1.5V/1.65V DD CMD[5] Input ...
Page 132
... B9 I/O C1 I/O C10 I/O C11 2.5V/3.3V C12 I/O C13 I/O C14 I/O C15 Input C16 I/O C17 I/O C18 2.5V/3.3V C19 CYNSE70128 Signal Name Signal Type DQ[06] I/O V 2.5V/3.3V DDQ DQ[00] I/O V 2.5V/3.3V DDQ V Ground SS V Ground SS DQ[70] I/O V 2.5V/3.3V DDQ ...
Page 133
... Ground G26 Ground G3 1.5V/1.65V G4 Output H1 Output H2 1.5V/1.65V H23 Ground H24 Ground H25 Ground H26 Ground H3 Ground H4 Ground J1 Input J2 2.5V/3.3V J23 CYNSE70128 Signal Name Signal Type TMS Input V 1.5V/1.65V DD V 1.5V/1.65V DD V 1.5V/1.65V DD V 1.5V/1.65V DD V 1.5V/1.65V DD SADR[01] Output V 2.5V/3.3V DDQ V 1.5V/1.65V ...
Page 134
... Ground P24 Ground P25 Ground P26 1.5V/1.65V U24 1.5V/1.65V U25 2.5V/3.3V U26 Ground U3 Ground U4 Ground V1 Ground V2 Ground V23 Ground V24 CYNSE70128 Signal Name Signal Type SADR[11] Output BHI[0] Input V 1.5V/1.65V DD V 1.5V/1.65V DD V 2.5V/3.3V DDQ SADR[17] Output V 1.5V/1.65V DD V 1.5V/1.65V DD BHI[1] ...
Page 135
... CYNSE70128–100BGC NSE Note: 27. All V pins should be set to 2.5V or 3.3V (CYNSE70128). DDQ Document #: 38-02040 Rev. *F © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...
Page 136
... Package Diagram Figure 20-1. 388-lead Ball Grid Array ( 2.33 mm) BG388 APT is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-02040 Rev. *F CYNSE70128 51-85103-*C Page 136 of 137 ...
Page 137
... Added Industrial parts ordering information. Removed Alternative power-up sequence instructions: TOC, Figure 13-3. Added 3.3V to the I/O Voltage of CYNSE70128-83BGI ordering information. Corrected Section 10.6.10 Figure Number Reference from Figure 12-37 to Figure 10-71. Corrected Section 10.6.10 Figure Number Reference from Figure 12-38 to Figure 10-72. ...