CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 113

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

12.6
SRAM Write enables Write access to the off-chip SRAM that contains associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend
on the TLSZ value parameter programmed in the device configuration register. The following explains the SRAM Write operation
accomplished with a table of only one device of the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1.
Figure 12-8 shows the timing diagram. For the following description the selected device refers to the only device in the table as
it is the only device that will be accessed.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation. The Write cycle appears at the SRAM bus,
however, with the same latency as that of a Search instruction, as measured from the second cycle of the Write command.
Document #: 38-02040 Rev. *F
TLSZ = 10, HLAT = 010, LRAM = 1, LDEV = 1.
• Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0], using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device.
• Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device.
DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[23:21] on CMD[8:6] in this cycle.
because burst Writes into the SRAM are not supported.
address with DQ[20:19] set to 10 to select the SRAM address.
Writes into the SRAM are not supported.
Figure 12-7. SRAM Read Through Device Number 0 in a Block of 31 Devices (Device Number 30 Timing)
SRAM Write with a Table of One Device
SADR[23:0]
CMD[10:2]
CMD[1:0]
PHS_L
CMDV
CLK2X
ACK
ALE_L
OE_L
CE_L
SSV
WE_L
SSF
DQ
0
1
1
z
0
0
1
Address
cycle
1
A B
00
Read
cycle
2
cycle
3
cycle
4
Note
cycle
5
. CMD[2] must be set to 0 for SRAM Write because burst
cycle
6
cycle
Note
7
z
z
z
z
. CMD[2] must be set to 0 for SRAM Write
cycle
8
1
1
1
cycle
9
cycle
10
CYNSE70128
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