CY7C4285-15ASC Cypress Semiconductor Corp, CY7C4285-15ASC Datasheet - Page 8

• Manufacturer Part Number: CY7C4285-15ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4285-15ASC

• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 64Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 50mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Document #: 38-06008 Rev. *A
First Data Word Latency after Reset with Simultaneous Read and Write
Reset Timing
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
18. When t
19. The first word is available the cycle after EF goes HIGH, always.
REN, WEN,
Q
D
0
0
Q
WCLK
RCLK
EF,PAE
FF,PAF,
–D
WEN
–Q
0 –
REN
The Latency Timing applies only at the Empty Boundary (EF = LOW).
OE
EF
17
17
RS
Q
HF
LD
17
SKEW2
t
ENS
[16]
> minimum specification, t
t
DS
D
0
(FIRSTVALID WRITE)
(continued)
FRL
t
(maximum) = t
SKEW2
t
t
t
RSF
RSF
RSF
t
RS
t
OLZ
t
FRL
CLK
[18]
+ t
SKEW2
t
D
REF
. When t
1
SKEW2
t
OE
< minimum specification, t
t
RSR
t
D
A
2
FRL
(maximum) = either 2*t
D
0
t
A
[19]
D
3
CLK
+ t
OE=0
OE=1
SKEW2
CY7C4275
CY7C4285
[17]
or t
Page 8 of 21
CLK
4275–8
D
+ t
4275–9
1
SKEW2
D
4
.
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