CY7C4285-15ASC Cypress Semiconductor Corp, CY7C4285-15ASC Datasheet - Page 11

• Manufacturer Part Number: CY7C4285-15ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4285-15ASC

• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 64Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 50mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Document #: 38-06008 Rev. *A
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
Programmable Almost Full Flag Timing
Notes:
21. PAE offset
22. t
23. If a read is preformed on this rising edge of the read clock, there will be Empty + (n 1) words in the FIFO when PAE goes LOW.
24. PAF offset = m. Number of data words written into FIFO already = 32768
25. PAF is offset = m.
26. 32768 m words in CY7C4275 and 65536 – m words in CY7C4285.
27. 32768
PAF
rising RCLK is less than t
WCLK
WCLK
SKEW3
RCLK
RCLK
WEN
WEN
REN
PAE
REN
[25]
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
(m + 1) words in CY7C4275 and 65536 – (m + 1) CY7C4285.
n.
t
CLKH
SKEW3
, then PAE may not change state until the next RCLK.
(continued)
t
SKEW3
t
CLKH
t
ENS
[22]
t
ENH
t
CLKL
Note 24
Note 21
t
ENS
(m + 1) for the CY7C4285 and 65536
t
ENH
t
PAE synch
t
CLKL
t
PAF
t
t
ENS
ENS
FULL– M WORDS
N + 1 WORDS
IN FIFO
IN FIFO
t
ENS
[26]
t
PAF
t
ENH
(m + 1) for the CY7C4285.
FULL– (M+1) WORDS
Note 23
IN FIFO
CY7C4275
CY7C4285
Page 11 of 21
t
PAE synch
[27]
4275–14
4275–15
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