CY7C4285-15ASC Cypress Semiconductor Corp, CY7C4285-15ASC Datasheet - Page 3

• Manufacturer Part Number: CY7C4285-15ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4285-15ASC

• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 64Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 50mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Pin Definitions
Document #: 38-06008 Rev. *A
D
Q
WEN
REN
WCLK
RCLK
WXO/HF
EF
FF
PAE
PAF
LD
FL/RT
WXI
RXI
RXO
RS
OE
V
Signal Name
CC
0–17
0–17
/SMODE
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
Read Clock
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Load
First Load/
Retransmit
Write Expansion
Input
Read Expansion
Input
Read Expansion
Output
Reset
Output Enable
Synchronous
Almost Empty/
Almost Full Flags
Description
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Data inputs for an 18-bit bus
Data outputs for an 18-bit bus
Enables the WCLK input
Enables the RCLK input
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when V
to V
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
V
When LD is LOW, D
ble-flag-offset register.
Dual-Mode Pin:
Cascaded – The first device in the daisy chain will have FL tied to V
devices will have FL tied to V
to V
Not Cascaded – Tied to V
mode by strobing RT.
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to V
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to V
Cascaded – Connected to RXI of next device.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-
nected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Dual-Mode Pin
Asynchronous Almost Empty/Almost Full flags – tied to V
Synchronous Almost Empty/Almost Full flags – tied to V
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
CC
CC
; it is synchronized to WCLK when V
SS
; it is synchronized to RCLK when V
on all devices.
0–17
SS
(Q
SS
SS
. Retransmit function is also available in stand-alone
.
.
0–17
CC
) are written (read) into (from) the programma-
. In standard mode or width expansion, FL is tied
Function
CC
CC
/SMODE is tied to V
/SMODE is tied to V
CC
SS
.
CC
.
/SMODE is tied to
CC
SS
CY7C4275
CY7C4285
/SMODE is tied
SS
SS
.
; all other
.
Page 3 of 21
[+] Feedback