CY7C1363A-117AJC Cypress Semiconductor Corp, CY7C1363A-117AJC Datasheet
CY7C1363A-117AJC
Specifications of CY7C1363A-117AJC
Related parts for CY7C1363A-117AJC
CY7C1363A-117AJC Summary of contents
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... For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com for A version of TQFP (3 Chip Enable Option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable. 3 Cypress Semiconductor Corporation Document #: 38-05302 Rev. *B 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description The CY7C1361B/CY7C1363B ...
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Logic Block Diagram – CY7C1361B (256K x 36) ADDRESS A0, A1, A REGISTER MODE ADV CLK COUNTER AND LOGIC CLR ADSC ADSP DQ DQP , BYTE BYTE WRITE REGISTER WRITE REGISTER DQ DQP C , ...
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Pin Configurations 100-pin TQFP Pinout (3 Chip Enables) (A version) DQP DDQ V 5 SSQ SSQ ...
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Pin Configurations (continued) 100-pin TQFP (2 Chip Enables) (AJ Version) DQP DDQ V 5 SSQ SSQ ...
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Pin Configurations (continued DDQ DDQ DDQ DDQ DQ N ...
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Pin Configurations (continued 288M DQP DDQ DDQ DDQ F DQ ...
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... Byte Write Select Inputs, active LOW. Qual- ified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes ...
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CY7C1361B–Pin Definitions (continued) TQFP TQFP (3-Chip (2-Chip Name Enable) Enable ADSC 87 87 BWE 52,53,56,57, 52,53,56,57 58,59,62,63, 58,59,62,63, 68,69,72,73, 68,69,72,73, 74,75,78,79, 74,75,78,79, 2,3,6,7,8,9, 2,3,6,7,8,9, 12,13,18,19, 12,13,18,19, 22,23,24,25, 22,23,24,25, 28,29 28,29 51,80,1,30 51,80,1,30 P6,D6,D2, ...
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CY7C1361B–Pin Definitions (continued) TQFP TQFP (3-Chip (2-Chip Name Enable) Enable) V 17,40,67,90 17,40,67,90 H2,D3,E3 5,10,21,26, 5,10,21,26, SSQ 55,60,71,76 55,60,71,76 TDO – – TDI – – TMS – – TCK – – NC 16,38,39,42, 16,38,39,42, 66 43,66 V /DNU ...
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... CY7C1361B CY7C1363B Description Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW and BWE) ...
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CY7C1363B: Pin Definitions (continued) TQFP TQFP (3-Chip (2-Chip Name Enable) Enable ADSC 58,59,62,63, 58,59,62,63 68,69,72,73, 68,69,72,73, 8,9,12,13, 8,9,12,13, 18,19,22,23 18,19,22,23 74,24 74,24 DQP [A:B] MODE 15,41,65,91 15,41,65,91 C4,J2,J4 ...
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CY7C1363B: Pin Definitions (continued) TQFP TQFP (3-Chip (2-Chip Name Enable) Enable) V 17,40,67,90 17,40,67,90 D3,D5,E3 5,10,21,26, 5,10,21,26, SSQ 55,60,71,76, 55,60,71,76, TDO – – TDI – – TMS – – TCK – – NC 1,2,3,6,7,16, 1,2,3,6,7,16, 25,28,29,30, 25,28,29,30, 38,39,42,51, ...
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... Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed ...
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... The DQ pins are controlled by the current cycle and the OE signal asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE the ADSP or with the assertion of ADSC . As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state don't care for the remainder of the write cycle ...
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Partial Truth Table for Read/Write Function (CY7C1361B) Read Read Write Byte (A, DQP ) A Write Byte (B, DQP ) B Write Bytes (B, A, DQP , DQP ) A B Write Byte (C, DQP ) C Write Bytes (C, ...
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... TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK ...
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... The user must be aware that the TAP controller clock can only operate at a frequency MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies possible that during the Capture-DR state, an input or output will undergo a transition ...
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CLK captured in the boundary scan register. Once the data is captured possible to shift out the data by putting the TAP into the Shift-DR ...
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TAP AC Test Conditions Input pulse levels ........ ........................................V Input rise and fall times ...................... ..............................1ns Input timing reference levels ...........................................1.5V Output reference levels...................................................1.5V Test load termination supply voltage...............................1.5V 3.3V TAP AC Output Load Equivalent 1.5V TDO Z = ...
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... Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05302 Rev. *B CY7C1361B CY7C1363B (256Kx36) ...
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BGA Boundary Scan Order CY7C1361B (256K x 36) BALL Signal BIT# ID Name BIT# BALL ID 1 CLK BWE ADSC ...
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Boundary Scan Order CY7C1361B (256K x 36) BALL Signal BIT# ID Name BIT# BALL CLK BWE ADSC ADSP ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on V Relative to GND........ –0.5V to +4.6V ...
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Thermal Resistance Parameter Description Θ Thermal Resistance JA (Junction to Ambient) Θ Thermal Resistance JC (Junction to Case) [14] Capacitance Parameter Description C Input Capacitance IN C Clock Input Capacitance CLK C Input/Output Capacitance I/O AC Test Loads and ...
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... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1361B CY7C1363B 117 MHz 100 MHz Max ...
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Timing Diagrams [21] Read Cycle Timing t CYC CLK ADS t ADH ADSP ADSC ADDRESS WES WEH GW, BWE, CES t CEH CE ADV OE t ...
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Timing Diagrams (continued) [21, 22] Write Cycle Timing t CYC CLK ADS t ADH ADSP t ADS t ADH ADSC ADDRESS A1 A2 Byte write signals are ignored for first cycle ...
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Timing Diagrams (continued) [21, 23, 24] Read/Write Cycle Timing t CYC CLK ADS t ADH ADSP ADSC ADDRESS A1 A2 BWE CES t CEH CE ADV OE High-Z ...
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Timing Diagrams (continued) [25, 26] ZZ Mode Timing CLK ZZI I SUPPLY I DDZZ ALL INPUTS (except ZZ) Outputs (Q) Ordering Information Speed (MHz) Ordering Code 133 CY7C1361B-133AC CY7C1363B-133AC CY7C1361B-133AI CY7C1363B-133AI CY7C1361B-133AJC CY7C1363B-133AJC CY7C1361B-133AJI CY7C1363B-133AJI CY7C1361B-133BGC ...
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Ordering Information (continued) Speed (MHz) Ordering Code 117 CY7C1361B-117AC CY7C1363B-117AC CY7C1361B-117AI CY7C1363B-117AI CY7C1361B-117AJC CY7C1363B-117AJC CY7C1361B-117AJI CY7C1363B-117AJI CY7C1361B-117BGC CY7C1363B-117BGC CY7C1361B-117BGI CY7C1363B-117BGI CY7C1361B-117BZC CY7C1363B-117BZC CY7C1361B-117BZI CY7C1363B-117BZI 100 CY7C1361B-100AC CY7C1363B-100AC CY7C1361B-100AI CY7C1363B-100AI CY7C1361B-100AJC CY7C1363B-100AJC CY7C1361B-100AJI CY7C1363B-100AJI CY7C1361B-100BGC CY7C1363B-100BGC CY7C1361B-100BGI CY7C1363B-100BGI CY7C1361B-100BZC CY7C1363B-100BGC CY7C1361B-100BZI ...
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Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 16.00±0.20 14.00±0.10 100 0.08 MIN. 0° MIN. 0.20 MAX. 0.25 GAUGE PLANE R 0.08 MIN. 0°-7° 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 ...
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Package Diagrams (continued) Document #: 38-05302 Rev. *B 119-Lead PBGA ( 2.4 mm) BG119 CY7C1361B CY7C1363B 51-85115-*B Page [+] Feedback ...
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... Document #: 38-05302 Rev. *B © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...
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... Document History Page Document Title: CY7C1361B/CY7C1363B 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Document #: 38-05302 Rev. *B REV. ECN NO. Issue Date ** 116857 06/24/02 *A 206502 See ECN *B 225181 See ECN Document #: 38-05302 Rev. *B Orig. of Change Description of Change RCS New Data Sheet NJY Removed Preliminary status ...