CY7C1373B-100AC Cypress Semiconductor Corp, CY7C1373B-100AC Datasheet - Page 18

• Manufacturer Part Number: CY7C1373B-100AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1373B-100AC

• Density: 18Mb
• Access Time (max): 8.5ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 225mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05198 Rev. **
Switching Characteristics
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-Up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes:
17. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and
18. t
19. At any given voltage and temperature, t
20. This parameter is sampled and not 100% tested.
CYC
CH
CL
CO
EOV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
Parameter
output loading of the specified I
voltage.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
, t
CLZ
, t
EOV
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
Address Set-Up Before CLK Rise
Data Input Set-Up Before CLK Rise
CEN Set-Up Before CLK Rise
WE, BWS
ADV/LD Set-Up Before CLK Rise
Chip Select Set-Up
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BW
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
, t
EOLZ
, and t
X
Hold After CLK Rise
x
EOHZ
Set-Up Before CLK Rise
OL
Description
are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured 200 mV from steady-state
[15, 17, 18, 19, 20]
/I
[15, 17, 18, 19, 20]
OH
Over the Operating Range
and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
EOHZ
is less than t
[15, 18, 20]
[17, 18, 20]
[17, 18, 20]
EOLZ
and t
CHZ
is less than t
[17]
Min.
8.5
2.3
2.3
1.5
1.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0
–117
CLZ
Max.
7.5
3.4
3.0
4.0
to eliminate bus contention between SRAMs when sharing the same
Min.
10.0
2.5
2.5
1.5
1.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0
–100
Max.
8.5
3.8
3.0
4.0
Min.
12.0
3.0
3.0
1.5
1.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0
–83
CY7C1371B
CY7C1373B
Max.
10.0
4.2
3.0
4.0
Page 18 of 26
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns