CY7C1373B-100AC Cypress Semiconductor Corp, CY7C1373B-100AC Datasheet
CY7C1373B-100AC
Manufacturer Part Number
CY7C1373B-100AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheets
1.CY7C1373B-100AC.pdf
(26 pages)
2.CY7C1373B-100AC.pdf
(26 pages)
3.CY7C1373B-100AC.pdf
(26 pages)
Specifications of CY7C1373B-100AC
Density
18Mb
Access Time (max)
8.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TQFP
Operating Temp Range
0C to 70C
Supply Current
225mA
Operating Supply Voltage (min)
3.14V
Operating Supply Voltage (max)
3.63V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
18b
Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-05198 Rev. **
Features
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Logic Block Diagram
512K x 36/1M x 18 Flow-Thru SRAM with NoBL™ Architecture
• Pin compatible and functionally equivalent to ZBT
• Supports 117-MHz bus operations with zero wait states
• Internally self-timed output buffer control to eliminate
• Registered inputs for flow-thru operation
• Byte Write capability
• Common I/O architecture
• Fast clock-to-output times
• Single 3.3V –5% and +10% power supply V
• Separate V
• Clock enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP and 119 BGA packages
• Burst capability – linear or interleaved burst order
• JTAG boundary scan for BGA packaging version
• Automatic power down available using ZZ mode or CE
BWSX
devices
the need to use asynchronous OE
deselect
AX
DQX
— Data is transferred on every clock
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
— 10.0ns (for 83-MHz device)
DPX
X = a, b, c, d
X = a, b, c, d
X= a, b, c, d X = a, b
X = 18:0
CY7C1371
DDQ
for 3.3V or 2.5V I/O
X = a, b
X = a, b
X = 19:0
CY7C1373
ADV/LD
Mode
BWS
OE
CEN
CLK
WE
CE 1
CE 2
CE
A
x
3
x
•
3901 North First Street
DD
and Write
Control
Logic
117 MHz
250
7.5
20
Functional Description
The CY7C1371B/CY7C1373B is 3.3V, 512K × 36 and 1M × 18
synchronous flow-thru burst SRAMs, respectively designed to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1371B/
CY7C1373B is equipped with the advanced No Bus Latency™
(NoBL ) logic required to enable consecutive Read/Write
operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
Write/Read transitions.The CY7C1371B/CY7C1373B is pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 7.5 ns (117-MHz
device).
Write operations are controlled by the byte Write Selects
(BWS
a Write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed Write circuitry. ZZ may be tied
to LOW if it is not used.
Synchronous Chip enables (CE
on the BGA) and an asynchronous Output enable (OE)
provide for easy bank selection and output three-state control.
In order to avoid bus contention, the output drivers are
synchronously three-stated during the data portion of a Write
sequence.
a,b,c,d
•
100 MHz
225
8.5
20
San Jose
for CY7C1371B and BWS
CE
256K X 36/
512K X 18
Memory
Data-In REG.
Array
Q
D
•
83 MHz
CA 95134
10.0
185
20
1
, CE
Revised February 4, 2002
2
a,b
, CE
for CY7C1373B) and
CY7C1371B
CY7C1373B
3
•
on the TQFP, CE
408-943-2600
Unit
mA
mA
ns
DP
DQ
x
x
1
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