CY7C09179V-7AC Cypress Semiconductor Corp, CY7C09179V-7AC Datasheet - Page 17

• Manufacturer Part Number: CY7C09179V-7AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09179V-7AC

• Density: 288Kb
• Access Time (max): 18ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 45MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 15b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 275mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 9b
• Number Of Words: 32K
• Lead Free Status / Rohs Status: Not Compliant

Table 1. Read/Write and Enable Operation
Table 2. Address Counter Control Operation
Document #: 38-06043 Rev. *C
Address
Notes
34. “X” = “Don’t Care”, “H” = V
35. ADS, CNTEN, CNTRST = “Don’t Care.”
36. OE is an asynchronous input signal.
37. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
38. CE
39. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
40. Counter operation is independent of CE
OE
A
X
X
X
X
X
X
H
L
n
0
and OE = V
Previous
Address
A
A
X
X
CLK
n
n
X
IL
; CE
1
and R/W = V
CLK
IH
, “L” = V
Inputs
CE
H
X
L
L
L
ADS
IL
0
IH
X
H
H
L
.
.
0
and CE
CNTEN
X
X
H
L
1
CE
.
H
H
H
[34, 35, 36]
X
L
1
[34, 38, 39, 40]
L
H
H
H
CNTRST
R/W
H
X
X
L
X
D
D
D
D
out(0)
out(n)
out(n)
out(n+1)
I/O
High-Z
High-Z
D
D
High-Z
IN
OUT
I/O
Outputs
Increment
0
Mode
Reset
Load
Hold
–I/O
9
Counter Reset to Address 0
Address Load into Counter
External Address Blocked—Counter
Disabled
Counter Enabled—Internal Address
Generation
Deselected
Deselected
Write
Read
Outputs Disabled
CY7C09079V/89V/99V
CY7C09179V/89V/99V
[37]
Operation
[37]
[37]
Operation
Page 17 of 21
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