CY7C09179V-7AC Cypress Semiconductor Corp, CY7C09179V-7AC Datasheet

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... Automatic power down ■ Commercial and Industrial temperature ranges ■ Available in 100-pin TQFP ■ Pb-free packages available ■ I/O I/O Control Control True Dual-Ported RAM Array for 128K devices. • 198 Champion Court • San Jose CY7C09079V/89V/99V CY7C09179V/89V/99V R 0 0/1 FT/Pipe R 8/9 [2] I/O – ...

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... Functional Description The CY7C09079V/89V/99V and CY7C09179V/89V/99V are high speed synchronous CMOS 32K, 64K, and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any [4] location in memory. Registers on control, address, and data lines enable minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time ...

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... Pin Configurations (continued Figure 2. 100-Pin TQFP (Top View0 - CY7C09199V (128K x 9), CY7C09189V (64K x 9),CY7C09179V (32K x 9) 100 A7L 3 A8L 4 A9L 5 A10L 6 A11L 7 A12L 8 A13L 9 A14L 10 [8] A15L 11 [9] A16L 12 VCC CE0L 18 CE1L 19 CNTRSTL 20 R/WL 21 OEL 22 FT/PIPEL Document #: 38-06043 Rev CY7C09079V/89V/99V ...

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... FT/PIPE L R For pipelined mode operation, assert this pin HIGH. GND Ground Input Connect. V Power Input. CC Notes 8. This pin is NC for CY7C09179V. 9. This pin is NC for CY7C09179V and CY7C09189V Document #: 38-06043 Rev. *C CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V [1] [1] CY7C09179V/89V/99V-7 83 7.5 155 25 10 μA Description – ...

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... Industrial 10 Commercial 105 135 95 [11] Industrial 125 Test Conditions ° MHz 3.3V CC AND CE must be asserted to their active states ( CY7C09079V/89V/99V CY7C09179V/89V/99V Ambient Temperature V CC ° ° 3.3V ± 300 +70 C ° ° 3.3V ± 300 mV – +85 C [1] -9 -12 2.4 2.4 0.4 0.4 ...

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... TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) 3.0V 10% GND ≤ Figure 5. Load Derating Curve Capacitance (pF) CY7C09079V/89V/99V CY7C09179V/89V/99V 3. 590Ω OUTPUT 435Ω (c) Three-State Delay (Load 2) (Used for & t CKLZ OLZ OHZ including scope and jig) [13] ALL INPUT PULSES 90% 90% 10% ≤ ...

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... Write Port Clock HIGH to Read Data Delay CWDD t Clock to Clock Set-Up Time CCS Notes 14. Test conditions used are Load 2. 15. This parameter is guaranteed by design, but it is not production tested. Document #: 38-06043 Rev. *C CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V [1] [ Min Max Min Max Min Max ...

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... Addresses do not have to be accessed sequentially since ADS = V only. Document #: 38-06043 Rev. *C CYC1 t CL1 A A n+1 n following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference IL CY7C09079V/89V/99V CY7C09179V/89V/99V [16, 17, 18, 19 n+3 t CKHZ Q n+1 n OHZ OLZ t OE Page [+] Feedback ...

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... ADDRESS A (B1 0(B1) DATA OUT(B1 ADDRESS A (B2 0(B2 DATA OUT(B2) Document #: 38-06043 Rev CL2 A A n+1 n+2 t CD2 CKLZ [20, 21 CD2 CD2 HC CKHZ CKLZ CY7C09079V/89V/99V CY7C09179V/89V/99V [16, 17, 18 n+1 n+2 t OHZ t OLZ CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ Page [+] Feedback ...

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... CCS CD1 CWDD Document #: 38-06043 Rev MATCH t CD1 NO MATCH t CWDD VALID for the left port, which is being written to. IH CWDD CY7C09079V/89V/99V CY7C09179V/89V/99V [22, 23, 24, 25] t CD1 VALID (B1 >maximum specified, then data is not valid CCS Page [+] Feedback ...

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... Switching Waveforms (continued) Figure 10. Pipelined Read-to-Write-to-Read ( CYC2 t t CH2 CL2 CLK R ADDRESS DATA IN DATA OUT READ Document #: 38-06043 Rev n+1 n CD2 CKHZ OPERATION CY7C09079V/89V/99V CY7C09179V/89V/99V [19, 26, 27, 28 n+3 n CD2 CKLZ Q WRITE READ Page n+3 [+] Feedback ...

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... CNTEN, and CNTRST = 28. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document #: 38-06043 Rev n+1 n+2 n n+2 n+3 t CD2 OHZ WRITE . IH CY7C09079V/89V/99V CY7C09179V/89V/99V [19, 26, 27, 28 n+4 n CKLZ CD2 Q n+4 READ Page [+] Feedback ...

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... Q n DATA OUT OE Document #: 38-06043 Rev n+1 n+2 n n+2 t CD1 Q n+1 t CKHZ NO READ OPERATION n+1 n+2 n n+2 n OHZ READ WRITE CY7C09079V/89V/99V CY7C09179V/89V/99V [17, 19, 26, 27, 28 n+3 n CD1 CD1 Q n CKLZ DC WRITE READ [17, 20, 26, 27, 28 n+4 n CD1 t CD1 Q n CKLZ DC READ Page [+] Feedback ...

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... Document #: 38-06043 Rev SAD HAD t t SCN HCN t CD2 n+1 COUNTER HOLD READ WITH COUNTER Q n n+1 COUNTER HOLD READ WITH COUNTER . CY7C09079V/89V/99V CY7C09179V/89V/99V [29 n+2 n+3 READ WITH COUNTER [29 SAD HAD t t SCN HCN Q Q n+3 n+2 READ WITH COUNTER Page ...

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... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06043 Rev n n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD and equals the counter output when ADS = V IL CY7C09079V/89V/99V CY7C09179V/89V/99V [30, 31 n+2 n+3 n n+3 n+4 WRITE WITH COUNTER . IH Page ...

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... SD DATA DATA OUT COUNTER RESET Notes 32 33. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06043 Rev WRITE READ ADDRESS 0 ADDRESS 0 ADDRESS 1 CY7C09079V/89V/99V CY7C09179V/89V/99V [19, 26, 32 READ READ ADDRESS n Page [+] Feedback ...

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... CNTRST I/O Mode Reset out( Load out( Hold out( Increment out(n+ CY7C09079V/89V/99V CY7C09179V/89V/99V Operation [37] Deselected [37] Deselected Write [37] Read Outputs Disabled Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Page [+] Feedback ...

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... CY7C09099V-9AC CY7C09099V-9AI 12 CY7C09099V-12AC CY7C09099V-12AXC 32K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09179V-6AC CY7C09179V-6AXC [1] 7.5 CY7C09179V-7AC 9 CY7C09179V-9C 12 CY7C09179V-12AC CY7C09179V-12AXC Document #: 38-06043 Rev. *C Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack ...

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... Pb-Free Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Pb-Free Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Pb-Free Thin Quad Flat Pack CY7C09079V/89V/99V CY7C09179V/89V/99V Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Operating Range Commercial ...

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... Package Diagram Figure 18. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 (51-85048) Document #: 38-06043 Rev. *C CY7C09079V/89V/99V CY7C09179V/89V/99V 51-85048-*B Page [+] Feedback ...

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... Document History Page Document Title: CY7C09079V/89V/99V, CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9Synchronous Dual Port Static RAM Document Number: 38-06043 Orig. of Orig. of Rev. ECN No. Change Change ** 110191 SZV 09/29/01 *A 122293 RBI 12/27/02 *B 365034 PCN See ECN *C 2623658 VKN/PYRS 12/17/08 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’ ...