CY7C027-20AC Cypress Semiconductor Corp, CY7C027-20AC Datasheet - Page 10

• Manufacturer Part Number: CY7C027-20AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C027-20AC

• Density: 512Kb
• Access Time (max): 20ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 15b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 265mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 16b
• Number Of Words: 32K
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Document #: 38-06042 Rev. *D
Notes
CE
28. R/W must be HIGH during all address transitions.
29. A write occurs during the overlap (t
30. t
31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
32. To access RAM, CE = V
33. To access upper byte, CE = V
34. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
to be placed on the bus for the required t
as short as the specified t
To access lower byte, CE = V
[32,33]
HA
[32,33]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
R/W
R/W
OE
IL
PWE
, SEM = V
IL
.
IL
Figure 8. Write Cycle No. 2: CE Controlled Timing
t
t
, LB = V
, UB = V
SA
SA
Figure 7. Write Cycle No. 1: R/W Controlled Timing
NOTE 35
(continued)
SCE
IH
.
IL
or t
IL
SD
, SEM = V
, SEM = V
PWE
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
) of a LOW CE or SEM and a LOW UB or LB.
t
HZWE
IH
IH
.
.
[34]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[31]
t
t
SD
SD
PWE
or (t
[28, 29, 30, 34, 35]
HZWE
t
t
HA
HA
[28, 29, 30, 31]
t
t
+ t
HD
HD
t
SD
LZWE
) to allow the I/O drivers to turn off and data
t
HZOE
[34]
NOTE 35
CY7C027/028
CY7C037/038
Page 10 of 19
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