CY39200V388-181MGC Cypress Semiconductor Corp, CY39200V388-181MGC Datasheet - Page 85

• Manufacturer Part Number: CY39200V388-181MGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY39200V388-181MGC

• Family Name: Delta39K
• Memory Type: SRAM
• # Macrocells: 3072
• Number Of Usable Gates: 200000
• Propagation Delay Time: 8.5ns
• # I/os (max): 294
• Operating Supply Voltage (typ): 2.5/3.3V
• Ram Bits: 491520
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Document History Page=
Document #: 38-03039 Rev. *I
REV.
Document Title: Delta39K™ ISR™ CPLD Family CPLDs at FPGA Densities™
Document Number: 38-03039
*A
*B
*C
*D
*E
*G
*H
*F
**
ECN NO.
106503
107625
109681
121063
122543
128684
112376
112946
117518
05/30/01
12/21/01
04/04/02
10/04/02
12/10/02
08/04/03
07/11/01
11/16/01
11/06/02
Issue
Date
Change
Orig. of
OOR
OOR
DSG
SZV
RN
RN
RN
RN
RN
Change from Spec #: 38-00830 to 38-03039
Deleted 39K15 device and the associated -250-MHz bin specs
Deleted 144FBGA package and associated part numbers
Changed ESD spec from “MIL-STD-883” to “JEDEC EIA/JESD22-A114-A”
Changed the Prime bin for 39K50 and 39K30 from “MHz” to “233 MHz”
Changed the part ordering information accordingly
Updated the -233-MHz timing specs to match modified timing specs achieved by
design (main affected params: t
t
Updated I/O standard Timing Delay Specs and changed the default I/O standard
from 3.3V PCI to LVCMOS
Added paragraph about Delta39K being CompactPCI hot swap Ready
Added X8 mode in the PLL description
Added Standby ICC spec
Updated the recommended boot PROM for 39K165/200 to be CY3LV002 instead
of CY3LV020
Updated Delta39K family offering
Modified PLL timing parameters t
parameter
Deleted exception to CompactPCI Hot Swap compliance regarding “PCI
buffers....”
Added reference to app note “Hot Socketing Delta39K”
Revised CompactPCI Hot Swap Specification R1.0 to be R2.0
Combined with spec# 38-03040
Updated pin tables for 39K30 (208PQFP, 256FBGA)
Updated pin tables for 39K50 (208PQFP, 256/484FBGA, 388BGA)
Added X3, X5, X6, X16 multiplication modes to Spread Aware PLL
Added PLL parameters (f
Added and updated Storage Temperature for 39K200-208EQFP
Changed the I
Updated tCLZ, tCHMCYC2 parameter Values for -233 MHz bin
Updated Input and Output Standard Timing Delay Adjustment table
Removed Self Boot Industrial parts from the offering
Removed Delta39K165Z (1.8V) from the offering
Removed 144-FBGA package offering
Added self-boot Flash Memory endurance and data retention data
Added Family, Package, and Density Migration section
Added note 20 to 484/676 FBGA pin table to identify slow 39K165 IOs
Changed data sheet status from Preliminary to Final
Added note 7 to DC Characteristics
Updated spec 51-85103 (MG388 package drawing) to rev. *C
Changed the definition of following pins on CY39030 -256FBGA package:
Pin A10: From IO/Vref7 to IO/Vref6
Pin B7: From IO/Vref6 to V
Added Table to identify Bank Location of Global Clock and Global Control Pins
Removed all “Z” parts (1.8V)
Referenced EEPROM to ATMEL part number
CLMCYC2
, t
CHMCYC2
cc0
spec for 39K165 and 39K200
, t
CHMCLK
PLLVCO
CC
Description of Change
)
PD
DWSA
, P
, t
SAPLLI
MCCO
, t
DWOSA
, f
, t
MPPLI
IOS
, t
, t
Delta39K™ ISR™
MCCJ
SCS
)
, t
, and t
SCS2
CPLD Family
LOCK
, f
MAX2
. Added t
, t
Page 85 of 86
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