CY39200V388-181MGC Cypress Semiconductor Corp, CY39200V388-181MGC Datasheet - Page 23

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CY39200V388-181MGC

Manufacturer Part Number
CY39200V388-181MGC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY39200V388-181MGC

Family Name
Delta39K
Memory Type
SRAM
# Macrocells
3072
Number Of Usable Gates
200000
Propagation Delay Time
8.5ns
# I/os (max)
294
Operating Supply Voltage (typ)
2.5/3.3V
Ram Bits
491520
In System Programmable
Yes
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Lead Free Status / Rohs Status
Not Compliant

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Cluster Memory Timing Parameter Values
Channel Memory Timing Parameter Values
Document #: 38-03039 Rev. *I
t
t
t
t
t
t
Synchronous Mode Parameters
t
t
t
t
t
t
t
t
t
t
t
Dual-Port Asynchronous Mode Parameters
t
t
t
t
t
t
t
CLMAA
CLMPWE
CLMSA
CLMHA
CLMSD
CLMHD
CLMCYC1
CLMCYC2
CLMS
CLMH
CLMDV1
CLMDV2
CLMMACS1
CLMMACS2
MACCLMS1
MACCLMS2
CLMCLAA
CHMAA
CHMPWE
CHMSA
CHMHA
CHMSD
CHMHD
CHMBA
Asynchronous Mode Parameters
Internal Parameters
Parameter
Parameter
I/O Standard
SSTL2 II
HSTL IV
SSTL2 I
HSTL III
HSTL II
HSTL I
Min.
5.5
1.8
0.9
5.5
0.4
9.5
5.0
2.8
7.7
4.5
3.6
6.0
Min.
0
6
5.5
1.8
0.9
5.5
0.4
t
–0.02
–0.22
IOD
233
0.94
0.79
0.77
0.44
233
Max.
Fast Slew Rate
10.2
7.0
10
Max.
8.5
10
t
EA
0.4
0.2
0.9
0.8
0.5
0.6
Min.
2.0
1.0
6.0
0.5
5.0
3.0
8.0
5.0
4.0
6.5
10
Min.
6
0
6
6.0
2.0
1.0
6.0
0.5
Output Delay Adjustments
t
200
ER
200
0.5
0.5
0.1
0
0
0
Max.
7.5
Max.
11
11
9.0
11
(additional delay to fast slew rate)
Over the Operating Range
t
IODSLOW
Over the Operating Range
2.0
2.0
2.0
2.0
2.0
2.0
Min.
10.5
6.5
2.2
1.1
6.5
0.6
5.5
3.8
8.5
5.5
4.4
7.0
6.5
Min.
6.5
2.2
1.1
6.5
0.6
0
Slow Slew Rate
181
181
t
Max.
EASLOW
Max.
8.0
10.0
12
12
12
2.0
2.0
2.0
2.0
2.0
2.0
Min.
3.2
1.8
0.9
8.0
4.0
8.0
6.6
Min.
10
10
15
12
10
10
t
3.2
1.8
0.9
0
10
10
ERSLOW
2.0
2.0
2.0
2.0
2.0
2.0
125
125
Max.
Max.
14.0
17
17
10
17
t
Delta39K™ ISR™
IOIN
Input Delay Adjustments
0.9
0.9
0.5
0.5
0.5
0.5
Min.
10.0
4.0
2.0
1.0
5.0
8.0
12
12
20
15
10
12
12
Min.
0
4.0
2.0
1.0
12
12
CPLD Family
t
CKIN
83
83
0.5
0.5
0.5
0.5
0.5
0.5
Max.
Max.
16.0
20
20
15
20
Page 23 of 86
t
IOREGPIN
0.6
0.6
0.3
0.3
0.3
0.3
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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