CY39200V388-181MGC Cypress Semiconductor Corp, CY39200V388-181MGC Datasheet - Page 45

• Manufacturer Part Number: CY39200V388-181MGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY39200V388-181MGC

• Family Name: Delta39K
• Memory Type: SRAM
• # Macrocells: 3072
• Number Of Usable Gates: 200000
• Propagation Delay Time: 8.5ns
• # I/os (max): 294
• Operating Supply Voltage (typ): 2.5/3.3V
• Ram Bits: 491520
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Table 8. Pin Definition Table
Table 9. Mode Select (MSEL) Pin Connectivity Table
Table 11. 208 EQFP/PQFP Pin Table
Document #: 38-03039 Rev. *I
Note:
18. The PLL is available in Delta39K ‘V’ devices (2.5V/3.3V) and not in Delta39K ‘Z’ devices (1.8V). In Delta39K ‘Z’ devices, connect V
V
Config_Done
CCCNFG
V
GND
Pin Name
V
Reconfig
V
V
CCPLL
V
V
V
V
V
V
V
V
CCCNFG
TCLK
CCLK
Reset
CCJTAG
CCPRG
TDO
TMS
CCE
Data
V
CCIO0
CCIO1
CCIO2
CCIO3
CCIO4
CCIO5
CCIO6
CCIO7
TDI
CC
Pin
10
11
[18]
1
2
3
4
5
6
7
8
9
Delta39K - with external boot PROM
Delta39K - Self-Boot™ Solution
Function
Output
Output
Output
Output
Output
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Input
Input
Input
Input
Input
CY39030
IO/V
GCLK0
GCTL0
V
GND
GND
CCIO0
IO0
IO0
IO0
IO0
IO0
Pin to start configuration of Delta39K
JTAG Test Clock
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
Operating Voltage
V
V
V
V
V
V
V
V
V
V
V
V
Flag indicating that configuration is complete
Configuration Clock for serial interface with the external boot PROM
Chip select for the external boot PROM (active low)
Pin to receive configuration data from the external boot PROM
Reset signal to interface with the external boot PROM
REF0
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
for I/O bank 0
for I/O bank 1
for I/O bank 2
for I/O bank 3
for I/O bank 4
for I/O bank 5
for I/O bank 6
for I/O bank 7
for JTAG pins
for Configuration port
for PLL
for programming the Self-Boot™ solution embedded boot PROM
CY39050
IO/V
GCTL0
GCLK0
V
GND
GND
CCIO0
IO0
IO0
IO0
IO0
IO0
REF0
Table 10. I/O Banks for Global Clock and Global Control
Pins (in all densities and packages)
Number
Bank
Description
GCLK[0]
GCTL[0]
0
CY39100
IO/V
GCLK0
GCTL0
V
GND
GND
CCIO0
IO0
IO0
IO0
IO0
IO0
REF0
GCLK[1]
GCTL[1]
Delta39K™ ISR™
5
CPLD Family
GCLK[2]
GCTL[2]
CCPLL
6
CY39200
IO/V
GCTL0
GCLK0
V
GND
GND
to V
CCIO0
IO0
IO0
IO0
IO0
IO0
Page 45 of 86
REF0
CC
GCLK[3]
GCTL[3]
.
7