CY7C371I-66JC Cypress Semiconductor Corp, CY7C371I-66JC Datasheet - Page 2

• Manufacturer Part Number: CY7C371I-66JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C371I-66JC

• Family Name: FLASH370i
• Memory Type: Flash
• # Macrocells: 32
• Number Of Usable Gates: 800
• Propagation Delay Time: 15ns
• Number Of Logic Blocks/elements: 2
• # I/os (max): 32
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-03032 Rev. *A
Pin Configurations
Functional Description
Finally, the CY7C371i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing param-
eters on the CY7C371i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the F
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in a
single pass through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the F
handled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C371i has a separate
associated I/O pin. The input to the macrocell is the sum of
LASH
LASH
370i family. The CY7C371i includes two logic blocks.
I/O
370i CPLDs. Note that product term allocation is
CLK
5
/SCLK
ISR
I/O
I/O
GND
I/O
I/O
I/O
I/O
0
/I
EN
10
11
I
6
7
0
1
8
9
7
8
9
10
11
12
13
14
15
16
17
18
6 5
19 20
4
21
3
Top View
22
PLCC
2
LASH
23 24
1 44
370i logic block includes
25
43 42
26
27
41
USE ULTRA37000™ FOR
28
40
39
38
37
36
35
34
33
32
31
30
29
ALL NEW DESIGNS
I/O
I/O
I/O
I/O
CLK
GND
I
I
I/O
I/O
I/O
3
2
27
26
25
24
23
22
21
1
/SDI
/I
4
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed. It also has polarity control, and two global
clocks to trigger the register. The macrocell also features a
separate feedback path to the PIM so that the register can be
buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
two logic blocks on the CY7C371i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with F
PCI Compliance
The F
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term distri-
bution.
3.3V or 5.0V I/O Operation
The F
3.3V and 5.0V systems. All devices have two sets of V
one set, V
another set, V
always be connected to a 5.0V power supply. However, the
V
supply, depending on the output requirements. When V
pins are connected to a 5.0V source, the I/O voltage levels are
LASH
CCIO
I/O
CLK
5
/SCLK
ISR
LASH
I/O
I/O
GND
370i ensures compliance with the PCI AC specifications
LASH
I/O
I/O
I/O
I/O
pins may be connected to either a 3.3V or 5.0V power
0
EN
/I
10
11
I
6
7
0
1
8
9
370i family of CMOS CPLDs are fully compliant with
CCINT
370i family can be configured to operate in both
1
2
3
4
5
6
7
8
9
10
11
CCIO
44 43 42
12
, for internal operation and input buffers, and
13 14 15
, for I/O output drivers. V
41
Top View
16
TQFP
40
39 38 37
17
18 19 20
36
21
35
22
34
33
32
31
30
29
28
27
26
25
24
23
CY7C371i
I/O
I/O
I/O
I/O
CLK
GND
I
I
I/O
I/O
I/O
CCINT
3
2
27
26
25
24
23
22
21
1
Page 2 of 12
/SDI
/I
LASH
4
pins must
LASH
370i.”
CC
pins:
CCIO
370i