CY7C371I-66JC Cypress Semiconductor Corp, CY7C371I-66JC Datasheet

CY7C371I-66JC

Manufacturer Part Number
CY7C371I-66JC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C371I-66JC

Family Name
FLASH370i
Memory Type
Flash
# Macrocells
32
Number Of Usable Gates
800
Propagation Delay Time
15ns
Number Of Logic Blocks/elements
2
# I/os (max)
32
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C371I-66JC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Cypress Semiconductor Corporation
Document #: 38-03032 Rev. *A
Features
Functional Description
The CY7C371i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
all members of the F
Selection Guide
Logic Block Diagram
Maximum Propagation Delay
Minimum Set-up, t
Maximum Clock to Output
Typical Supply Current, I
Note:
• 32 macrocells in two logic blocks
• 32 I/O pins
• Five dedicated inputs including two clock pins
• In-System Reprogrammable (ISR™) Flash technology
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
• Fully PCI-compliant
• 3.3V or 5.0V I/O operation
• Available in 44-pin PLCC, and TQFP packages
• Pin-compatible with the CY7C372i
1. The 3.3V I/O mode timing adder, t
LASH
— JTAG interface
— f
— t
— t
— t
370i™ family of high-density, high-speed CPLDs. Like
I/O
MAX
PD
S
CO
= 5 ns
0
= 8.5 n3s
–I/O
= 6 ns
= 143 MHz
15
16 I/Os
S
CC
LASH
Comm./Ind.
[1]
, t
370i family, the CY7C371i is
[1]
3.3IO
CO
, t
PD
, must be added to this specification when V
BLOCK
LOGIC
2
16
A
7C371i-143 7C371i-110 7C371i-83 7C371iL-83 7C371i-66 7C371iL-66
MACROCELLS
8.5
75
5
6
3901 North First Street
INPUT
UltraLogic™ 32-Macrocell Flash CPLD
36
16
USE ULTRA37000™ FOR
ALL NEW DESIGNS
6.5
Inputs
10
75
3
6
PIM
Clock
Inputs
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ F
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
because of the superior routability of the F
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
The 32 macrocells in the CY7C371i are divided between two
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the F
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Like all members of the F
in I/O resources. Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins on the CY7C371i.
In addition, there are three dedicated inputs and two
input/clock pins.
CCIO
12
75
INPUT/CLOCK
MACROCELLS
8
8
2
= 3.3V.
36
16
San Jose
12
45
8
8
BLOCK
LOGIC
16
B
2
,
LASH
LASH
CA 95134
LASH
15
10
10
75
370i architecture are connected
370i family, the CY7C371i is rich
370i devices, the CY7C371i
16 I/Os
Revised April 19, 2004
15
10
10
45
LASH
EN
I/O
CY7C371i
408-943-2600
). Additionally,
16
370i devices,
–I/O
31
Unit
mA
ns
ns
ns

Related parts for CY7C371I-66JC

CY7C371I-66JC Summary of contents

Page 1

... Like all members of the F in I/O resources. Each macrocell in the device features an associated I/O pin, resulting in 32 I/O pins on the CY7C371i. In addition, there are three dedicated inputs and two input/clock pins. Clock ...

Page 2

... I/O pin is used as an input. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the two logic blocks on the CY7C371i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM ...

Page 3

... V Design Tools Development software for the CY7C371i is available from Cypress’s Warp™, Warp Professional™, and Warp Enter- prise™ software packages. Please refer to the data sheets on these products for more details. Cypress also actively supports almost all third-party design tools ...

Page 4

... Min 2. Max Max. CC Test Conditions V = 5.0V at f=1 MHz 5. MHz CCINT CY7C371i Ambient Temperature CCINT 5V ± 0.25V 5V ± 0.25V or 0°C to +70°C 3.3V ± 0.3V −40°C to +85°C 5V ± 0.5V 5V ± 0.5V or 3.3V ± 0.3V Min. Typ. [4] 2.4 [4,5] [4,5] ...

Page 5

... INCLUDING JIG AND (b) SCOPE 3.0V GND 2.08V(COM'L) < 2.13V(MIL) Output Waveform Measurement Level V OH 0. 0.5V measured with 35-pF AC Test Load. EA CY7C371i 44-Lead TQFP 44-Lead PLCC 2 5 Max. 100 170Ω (COM'L) 236Ω (MIL) ALL INPUT PULSES 90% 90% 10% ( Unit nH Unit ...

Page 6

... All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 13. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C371i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. ...

Page 7

... Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS [12] 7C371i−143 7C371i−110 Min. Max. [8] 8 [8] 10 [1] 14 [8] 8 [8] 10 [1] 14 500 PDL CY7C371i 7C371i−83 7C371i−66 7C371iL−83 7C371iL−66 Min. Max. Min. Max. Min 500 500 500 ...

Page 8

... LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS t ICS PDL ICOL t ICS t WH CY7C371i t SCS t ICO PDLL Page ...

Page 9

... REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS Ordering Information Speed (MHz) Ordering Code 143 CY7C371i−143AC CY7C371i−143JC 110 CY7C371i−110AC CY7C371i−110JC CY7C371i–110AI CY7C371i–110JI Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Package Name Package Type ...

Page 10

... CY7C371i−83JI CY7C371iL−83AC CY7C371iL−83JC CY7C371iL−83AI CY7C371iL−83JI 66 CY7C371i−66AC CY7C371i−66JC CY7C371i−66AI CY7C371i−66JI CY7C371iL−66AC CY7C371iL−66JC CY7C371iL−66AI CY7C371iL−66JI Package Diagrams Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Package Name Package Type ...

Page 11

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS 44-Lead Plastic Leaded Chip Carrier J67 CY7C371i 51-85003-*A Page ...

Page 12

... Document History Page Document Title: CY7C371i UltraLogic™ 32-Macrocell Flash CPLD Document Number: 38-03032 REV. ECN NO. Issue Date ** 106377 06/18/01 *A 213375 See ECN Document #: 38-03032 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Orig. of Change SZV Changed from Spec #: 38-00497 to 38-03032 FSG Added note to title page: “ ...

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