TE28F800F3B95 Intel, TE28F800F3B95 Datasheet - Page 11

• Manufacturer Part Number: TE28F800F3B95
• Manufacturer: Intel

Specifications of TE28F800F3B95

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

2.3
2.3.1
2.3.2
PRELIMINARY
WE#
WP#
WAIT#
V
V
V
GND
NC
PP
CC
CCQ
Sym
Table 1. Pin Descriptions (Sheet 2 of 2)
INPUT
INPUT
OUTPUT
SUPPLY
SUPPLY
SUPPLY
SUPPLY
Type
Memory Blocking Organization
The 3 Volt Fast Boot Block Flash memory family is an asymmetrically-blocked architecture that
enables system integration of code and data within a single flash device. For the address locations
of each block, see the memory maps in
Map” on page
Parameter Blocks
The 3 Volt Fast Boot Block Flash memory architecture includes parameter blocks to facilitate
storage of frequently updated small parameters that would normally be stored in an EEPROM. By
using software techniques, the word-rewrite functionality of EEPROMs can be emulated. Each
8- Mbit device contains eight 4-Kwords (4,096-words) parameter blocks.
Main Blocks
After the parameter blocks, the remainder of the array is divided into equal size main blocks for
code and/or data storage. The main blocks are the area of the device that support four-, eight-, and
continuous burst operations. The 8-Mbit device contains fifteen 32-Kword (32,768-word) main
blocks.
WRITE ENABLE: Controls writes to the CUI and array. Addresses and data are latched on the rising
edge of the WE# pulse.
WRITE PROTECTION: Provides a method for locking and unlocking all main blocks and two
parameter blocks.
When WP# is at logic low, lockable blocks are locked. If a program or erase operation is attempted on
a locked block, SR.1 and either SR.4 [program] or SR.5 [block erase] will be set to indicate the
operation failed.
When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased.
WAIT: Provides data valid feedback only when configured for synchronous burst mode and the burst
length is set to continuous. This signal is gated by OE# and CE# and is internally pull-up to V
resistor. WAIT# from several components can be tied together to form one system WAIT# signal.
BLOCK ERASE AND PROGRAM POWER SUPPLY (3.0 V–3.6 V, 11.4 V–12.6 V): For erasing array
blocks or programming data, a valid voltage must be applied to this pin. With V
contents cannot be altered. Block erase and program with an invalid V
attempted.
Applying 11.4 V–12.6 V to V
2500 cycles on the parameter blocks. V
(see
DEVICE POWER SUPPLY (3.0 V–3.6 V): With V
inhibited. Device operations at invalid V
OUTPUT POWER SUPPLY (3.0 V–3.6 V): Enables all outputs to be driven to 3.0 V to 3.6 V.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internally connected; it may be driven or floated. (Pins noted as possible
upgrades to 32-Mbit and 64-Mbit densities can be connected to the appropriate address lines to pre-
enable designs for possible future devices.).
Section 6.0
6. 8-Mbit Top Boot and Bottom Boot Blocking.
for details).
PP
can only be done for a maximum of 1000 cycles on main blocks and
Figure 3, “8- Mbit Top Boot and Bottom Boot Memory
PP
CC
Name and Function
may be connected to 12 V for a total of 80 hours maximum
voltages should not be attempted.
CC
V
LKO
, all write attempts to the flash memory are
PP
28F800F3—Automotive
voltage should not be
PP
V
PPLK
, memory
CCQ
via a
5