LH28F016SCHR-L95 Sharp Electronics, LH28F016SCHR-L95 Datasheet - Page 6

• Manufacturer Part Number: LH28F016SCHR-L95
• Manufacturer: Sharp Electronics

Specifications of LH28F016SCHR-L95

• Cell Type: NOR
• Density: 16Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

LH28F016SCT
Read
be read from any block, independent of the V
age. RP can be either V
command (Read Array, Read Identifier Codes, or Read
Status Register) to the CUI. Upon initial device power-
up or after exit from deep power-down mode, the
device automatically resets to Read Array mode. Four
control pins dictate the data flow in and out of the
device: CE , OE, WE, RP, and RP. CE and OE must be
driven active to obtain data at the outputs. CE is the
device selection control and when active enables the
selected memory device. OE is the data output (DQ
DQ
memory data onto the I/O bus. WE must be at V
V
Output Disable
puts are disabled. Output pins DQ
a high-impedance state.
Standby
standby mode which substantially reduces device
power consumption. DQ
high-impedance state independent of OE. If deselected
during block erase, byte write, or lock-bit configuration,
the device continues functioning, and consuming
active power until the operation completes.
Deep Power-down
places output drivers in a high-impedance state and
turns off all internal circuits. RP must be held LOW for
a minimum of 100 ns. Time t
return from power-down mode until initial memory
access outputs are valid. After this wake-up interval,
normal operation is restored. The CUI is reset to Read
Array mode and status register is set to 80H.
tion modes, RP at LOW will abort the operation. RY/BY
remains LOW until the Reset operation is complete.
Memory contents in the process of being altered are no
longer valid; data may be partially erased or written.
Time t
another command can be written.
assert RP during system reset. When the system
comes out of Reset, it expects to read from the flash
memory. Automated flash memories provide status
6
HH
Information, identifier codes, or a status register can
The first task is to write the appropriate read mode
With OE at a logic-high level (V
CE at a logic-high level (V
RP at V
In read modes, RP LOW deselects the memory,
During block erase, byte write, or lock bit configura-
As with any automated device, it is important to
0
. See Figure 15 for Read Cycle waveforms.
) control and when active, drives the selected
PHWL
IL
is required after RP goes HIGH (V
initiates the deep power-down mode.
IH
7
- DQ
or V
PHQV
IH
0
HH
outputs are placed in a
) places the device in
.
7
is required after the
IH
- DQ
), the device out-
0
are placed in
IH
PP
) before
IH
volt-
7
or
-
information when accessed during block erase, byte
write or block lock bit configuration. If a CPU reset
occurs with no flash memory reset, proper CPU initial-
ization may not occur because the flash memory may
be providing status information instead of array data.
SHARP’s flash memories allow proper CPU initializa-
tion following a system reset through the use of the RP
input. For this application, RP is controlled by the same
RESET signal that resets the system CPU.
Read Identifier Codes
manufacturer code, device code, block lock configura-
tion codes for each block, and the master lock configu-
ration code (see Figure 4). Using the manufacturer and
device codes, the system CPU can automatically match
the device with its proper algorithms. The block lock and
master lock configuration codes identify locked and
unlocked blocks and the master lock-bit setting.
The Read Identifier Codes operation outputs the
Figure 4. Device Identifier Code Memory Map
1FFFFF
01FFFF
00FFFF
1F0004
1F0003
1F0002
1F0000
010004
010003
010002
010001
010000
000004
000003
000002
000000
1F0001
000001
.
.
.
BLOCK 31 LOCK CONFIGURATION CODE
BLOCK 1 LOCK CONFIGURATION CODE
MASTER LOCK CONFIGURATION CODE
BLOCK 0 LOCK CONFIGURATION CODE
FUTURE IMPLEMENTATION
FUTURE IMPLEMENTATION
FUTURE IMPLEMENTATION
FUTURE IMPLEMENTATION
FUTURE IMPLEMENTATION
(BLOCKS 2 THROUGH 30)
MANUFACTURER CODE
RESERVED FOR
RESERVED FOR
RESERVED FOR
RESERVED FOR
RESERVED FOR
DEVICE CODE
16M Flash Memory
BLOCK 31
BLOCK 0
BLOCK 1
28F016SCT-L95-4
Data Sheet
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.
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