LH28F016SCHR-L95 Sharp Electronics, LH28F016SCHR-L95 Datasheet - Page 5

• Manufacturer Part Number: LH28F016SCHR-L95
• Manufacturer: Sharp Electronics

Specifications of LH28F016SCHR-L95

• Cell Type: NOR
• Density: 16Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

16M Flash Memory
WSM activity by providing both a hardware signal of
status (versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using RY/BY minimizes both
CPU overhead and system power consumption. When
LOW, RY/BY indicates that the WSM is performing a
block erase, byte write, or lock-bit configuration.
new command, block erase is suspended (and byte
write is inactive), byte is suspended, (and byte write is
inactive), byte write is suspended, or the device is in
deep power-down mode.
cal temperature range (0°C to 70°C) and V
voltage range of 4.75 V - 5.25 V. At lower V
the access times are 100 ns (4.5 V - 5.5 V), 120 ns
(3.0 V - 3.6 V) and 150 ns (2.7 V - 3.6 V).
stantially reduces active current when the device is in
static mode (address not switching). In APS mode, the
typical I
standby mode is enabled. When the RP pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection dur-
ing Reset. A reset time (t
going HIGH until outputs are valid. Likewise, the device
has a wake time (t
the CUI are recognized. With RP at GND, the WSM is
reset and the status register is cleared. The device is
available in 40-pin TSOP packaging. Pinout is as shown
in Figure 1.
PRINCIPLES OF OPERATION
includes an on-chip Write State Machine (WSM) to
manage block erase, byte write, and lock-bit configura-
tion functions. It allows for: 100% TTL-level control
inputs, fixed power supplies during block erasure, byte
write, and lock-bit configuration, and minimal process
overhead with RAM-like interface timings.
mode (see ‘Bus Operations’ section), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
through the Command User Interface (CUI), indepen-
dent of the V
successful block erase, byte writing, and lock-bit config-
uration. All functions associated with altering memory
contents-block erase, byte write, lock-bit configuration,
status, and identifier codes are accessed via the CUI
Data Sheet
The RY/BY output gives an additional indicator of
RY/BY HIGH indicates that the WSM is ready for a
The access time is 95 ns (t
The Automatic Power Savings (APS) feature sub-
When CE and RP pins are at V
The LH28F016SCT SmartVoltage flash memory
After initial device power-up or return from Reset
Status register and identifier codes can be accessed
CCR
current is 1 mA at 5 V V
PP
voltage. High voltage on V
PHEL
) from RP HIGH until writes to
PHQV
AVQV
) is required from RP
) over the commeri-
CC
CC
, the I
.
CC
PP
CC
CC
voltages,
enables
CMOS
supply
and verified through the status register.
sor write timings. The CUI contents serve as input to
the WSM, which controls the block erase, byte write,
and lock-bit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition, inter-
nal verification, and margining of data. Addresses and
data are internally latch during write cycles. Writing the
appropriate command outputs array data, accesses
the identifier codes, or outputs status register data.
block erase, byte write, and lock-bit configuration can
be stored in any block. This code is copied to and exe-
cuted from system RAM during flash memory updates.
After successful completion, reads are again possible
via the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read or write data from any other block. Byte write sus-
pend allows system software to suspend a byte write to
read data from any other flash memory array location.
Data Protection
may choose to make the V
(available only when memory block erase, byte writes,
or lock-bit configurations are required) or hardwired to
V
practice and encourages optimaization of the proces-
sor-memory interface.
altered. The CUI, with the two-step block erase, byte
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to V
are disabled when V
age V
ing capability provides additional protection from
inadvertent code or data alteration by gating block
erase, and byte write operations.
BUS OPERATION
system. All bus cycles to or from the flash memory con-
form to standard microprocessor bus cycles.
PPH1/2/3
Commands are written using standard microproces-
Interface software that initiates and polls progress of
Depending on the application, the system designer
When V
The local CPU reads and writes the flash memory in-
LKO
. The device accommodates either design
or when RP is at V
PP
≤ V
PPLK
CC
, memory contents cannot be
is below the write lockout volt-
PP
IL
. The device’s block lock-
power supply switchable
PP
. All write functions
LH28F016SCT
5