LH28F160BJHE-TTLZE Sharp Electronics, LH28F160BJHE-TTLZE Datasheet - Page 8
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LH28F160BJHE-TTLZE
Manufacturer Part Number
LH28F160BJHE-TTLZE
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F160BJHE-TTLZE.pdf
(44 pages)
Specifications of LH28F160BJHE-TTLZE
Cell Type
NOR
Density
16Mb
Access Time (max)
90ns
Interface Type
Parallel
Boot Type
Top
Address Bus
20b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
16b
Number Of Words
1M
Supply Current
30mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LH28F160BJHE-TTLZE
Manufacturer:
SHARP
Quantity:
100
DQ
Symbol
A
V
GND
WE#
WP#
CE#
OE#
V
RP#
0
0
NC
CCW
-A
-DQ
CC
19
15
OUTPUT
SUPPLY
SUPPLY
SUPPLY
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A
A
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data
during memory array, status register and identifier code read cycles. Data pins float to high-
impedance when the chip is deselected or outputs are disabled. Data is internally latched during a
write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.
RESET: Resets the device internal automation. RP#-high enables normal operation. When driven
low, RP# inhibits write operations which provides data protection during power transitions. Exit
from reset mode sets the device to read array mode. RP# must be V
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
the rising edge of the WE# pulse.
WRITE PROTECT: When WP# is V
V
blocks.
BLOCK ERASE, FULL CHIP ERASE, WORD WRITE OR LOCK-BIT CONFIGURATION
POWER SUPPLY: For erasing array blocks, writing words or configuring lock-bits. With
V
lock-bit configuration with an invalid V
results and should not be attempted. Applying 12V±0.3V to V
done for a maximum of 1000 cycles on each block. V
total of 80 hours maximum.
DEVICE POWER SUPPLY: Do not float any power pins. With V
the flash memory are inhibited. Device operations at invalid V
Characteristics) produce spurious results and should not be attempted.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
15
12
IH
CCW
-A
-A
, locked boot blocks can not be written or erased. WP# is not affected parameter and main
19
19
V
: Main Block Address.
: Boot and Parameter Block Address.
CCWLK
, memory contents cannot be altered. Block erase, full chip erase, word write and
Table 1. Pin Descriptions
IL
, boot blocks cannot be written or erased. When WP# is
Name and Function
CCW
(see 6.2.3 DC Characteristics) produce spurious
CCW
may be connected to 12V±0.3V for a
CCW
CC
voltage (see 6.2.3 DC
CC
IL
during erase/write can only be
during power-up.
V
LKO
, all write attempts to
Rev. 1.27