LH28F160BJHE-TTLZE Sharp Electronics, LH28F160BJHE-TTLZE Datasheet - Page 27

• Manufacturer Part Number: LH28F160BJHE-TTLZE
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJHE-TTLZE

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.
5.2 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1µF ceramic capacitor
connected between its V
V
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7µF
electrolytic capacitor should be placed at the array’s power
supply connection between V
capacitor will overcome voltage slumps caused by PC
board trace inductance.
5.3 V
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the V
supplies the memory cell current for word writing and
block erasing. Use similar trace widths and layout
considerations given to the V
V
voltage spikes and overshoots.
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
CCW
CCW
occur.
supply traces and decoupling will decrease V
and GND. These high-frequency, low inductance
CCW
Trace on Printed Circuit Boards
CCW
Power supply trace. The V
CC
and GND and between its
CC
CC
and GND. The bulk
power bus. Adequate
CCW
CCW
pin
5.4 V
Block erase, full chip erase, word write and lock-bit
configuration are not guaranteed if V
valid V
3.6V range, or RP# V
register bit SR.3 is set to "1" along with SR.4 or SR.5,
depending on the attempted operation. If RP# transitions
to V
lock-bit configuration, SR.7 will remain "0" until the reset
operation is complete. Then, the operation will abort and
the device will enter reset mode. The aborted operation
may leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP# transitions to V
the status register.
The CUI latches commands issued by system software and
is not altered by V
actions. Its state is read array mode upon power-up, after
exit from reset mode or after V
5.5 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erase, full chip erase, word write or lock-
bit configuration during power transitions. Upon power-
up, the device is indifferent as to which power supply
(V
the CUI to read array mode at power-up.
A system designer must guard against spurious writes for
V
both WE# and CE# must be low for a command write,
driving either to V
step command sequence architecture provides added level
of protection against data alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled while
RP#=V
5.6 Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory’s nonvolatility increases usable
battery life because data is retained when system power is
removed.
CC
CCW
IL
voltages above V
IL
CCWH1/2
during block erase, full chip erase, word write or
CC
or V
regardless of its control inputs state.
, V
CC
CCW
) powers-up first. Internal circuitry resets
range, V
IH
, RP# Transitions
CCW
will inhibit writes. The CUI’s two-
IH
LKO
. If V
CC
or CE# transitions or WSM
when V
falls outside of a valid 2.7V-
CCW
CC
transitions below V
error is detected, status
CCW
CCW
falls outside of a
is active. Since
Rev. 1.27
IL
LKO
clear
.