LH28F008BVT-BTL10 Sharp Electronics, LH28F008BVT-BTL10 Datasheet - Page 8

• Manufacturer Part Number: LH28F008BVT-BTL10
• Manufacturer: Sharp Electronics

Specifications of LH28F008BVT-BTL10

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

2 PRINCIPLES OF OPERATION
The LH28F008BVT-BTL10 Smart3 Flash memory
includes an on-chip WSM to manage block erase and byte
write functions. It allows for: 100% TTL-level control
inputs, fixed power supplies during block erasure and byte
write, and minimal processor overhead with RAM-like
interface timings.
After initial device power-up or return from deep power-
down mode (see Bus Operations), the device defaults to
read array mode. Manipulation of external memory control
pins allow array read, standby and output disable
operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
voltage on V
writing. All functions associated with altering memory
contents−block erase, byte write, status and identifier
codes−are accessed via the CUI and verified through the
status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase and byte write. The
internal algorithms are regulated by the WSM, including
pulse repetition, internal verification and margining of
data. Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block
erase and byte write can be stored in any block. This code
is copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Byte write suspend allows system software to
suspend a byte write to read data from any other flash
memory array location.
PP
enables successful block erasure and byte
PP
voltage. High
[
A
DFFFF
AFFFF
EFFFF
CFFFF
BFFFF
0DFFF
0BFFF
FFFFF
D0000
A0000
9FFFF
8FFFF
7FFFF
5FFFF
3FFFF
1FFFF
0A000
19
E0000
C0000
B0000
6FFFF
4FFFF
2FFFF
0FFFF
0E000
0C000
09FFF
07FFF
05FFF
03FFF
01FFF
F0000
90000
80000
70000
60000
50000
40000
30000
20000
10000
08000
06000
04000
02000
00000
-A
0
]
Figure 3. Memory Map
8K-byte Parameter Block
8K-byte Parameter Block
8K-byte Parameter Block
8K-byte Parameter Block
8K-byte Parameter Block
8K-byte Parameter Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
64K-byte Main Block
8K-byte Boot Block
8K-byte Boot Block
Bottom Boot
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
1
0
Rev. 1.1